Xilinx Platform Cable USB II Manual page 30

Table 6: JTAG/SPI/Slave Serial Port: 2-mm Connector Signals (Cont'd)
Pin
JTAG
Number
Configuration
10 TDI
13 PGND
14 HALT
4 –
6 –
8 –
10 –
13 –
14 –
4 –
6 –
DS593 (v1.2.1) March 17, 2011
MODE
SPI Slave-Serial
(1)
Programming Configuration
– –
– –
– –
SS –
SCK –
MISO –
MOSI –
PGND –
WP –
– PROG
– CCLK
www.xilinx.com
(2)
Direction
JTAG Test Data In. This pin outputs the
Out serial data stream transmitted to the TDI pin
on the first device in a JTAG chain.
JTAG Pseudo Ground. Use of this pin is
optional. PGND is pulled Low during JTAG
operations; otherwise, it is high-Z. This pin is
Out
connected to an open-drain driver and
requires a pull-up resistor on the target
(4)
system.
JTAG Halt. Use of this pin is optional. Host
applications can customize the behavior of
Out
this signal. See
iMPACT, page
SPI Select. This pin is the active-Low SPI
Out chip select signal and should be connected
(1)
to the S pin on the SPI flash device.
SPI Clock. This pin is the clock signal for
Out SPI operations and should be connected to
(1)
the C pin on the SPI flash PROM.
SPI Master-Input, Slave-Output. This pin
is the target serial output data stream and
In
should be connected to the Q
SPI flash device.
SPI Master-Output Slave-Input. This pin
outputs the target serial input data stream
Out
for SPI operations and should be connected
(1)
to the D pin on the SPI flash device.
SPI Pseudo Ground. PGND is pulled Low
during SPI operations; otherwise, it is high-
Z. When connected to PROG_B on an
FPGA, the FPGA will high-Z its SPI signals
Out
while the cable is programming the SPI
flash. This pin is connected to an open-drain
driver and requires a pull-up resistor on the
target system.
SPI Write Protect. This pin is reserved for
– future use. Do not connect for SPI
programming.
Slave Serial Configuration Reset. This pin
is used to force a reconfiguration of the
target FPGA(s) and should be connected to
Out the PROG_B pin of the target FPGA for a
single-device system, or to the PROG_B pin
of all FPGAs in parallel in a daisy-chain
configuration.
Slave Serial Configuration Clock. FPGAs
load one configuration bit per CCLK cycle in
Slave Serial mode. CCLK should be
Out connected to the CCLK pin on the target
FPGA for single-device configuration, or to
the CCLK pin of all FPGAs in parallel in a
daisy-chain configuration.
Platform Cable USB II
Description
HALT_INIT_WP Signal in
22.
(1)
pin on the
(4)
30