Input Receive Structure; Target Interface Receiver Topology - Xilinx Platform Cable USB II Manual

X-Ref Target - Figure 21

Input Receive Structure

Each input signal is routed through a NC7WZ07 ultra high-speed CMOS, open-drain receive buffer. Series-termination
resistors (499Ω) provide current limit protection for positive and negative excursions. Schottky diodes provide the input
buffers with undershoot protection. The receive buffers are biased by an internal 1.8V power supply. See
for V and V specifications. The receive buffers can tolerate voltages higher than the bias voltage without damage,
IL IH
compensating for target system drivers in multi-device chains where the last device in the chain might be referenced to a
voltage other than V (for example, the TDO output at the end of a JTAG chain).
REF
X-Ref Target - Figure 22
DS593 (v1.2.1) March 17, 2011
Figure 21: Output Drive Voltage vs. V
FPGA
Input
Figure 22: Target Interface Receiver Topology
V Voltage (VDC)
REF
To output buffer
NC7WZ07
499Ω
BAT54
www.xilinx.com
Platform Cable USB II
DS593_21_021408
REF
2 mm Connector
I/O Pin
DS593_22_021408
Table 9, page 32
21