Digi ConnectCore 6UL Hardware Design Manuallines page 7

Schematics design checklist
☑
Item
2. Minimum
decoupling
capacitors on
VSYS/VSYS2
3. VCC_MCA
power line
4. 3V3_EXT
power rail
5. VCC_ENET
power rail
6. Unconnected
power rails
ConnectCore 6UL Hardware Design Guidelines
Description
2 x 47uF + 1 x 4.7uF + 1 x 100nF
This power line is the input power supply of the on-module MCA. It must
be powered from a dedicated 3.3V regulator connected to the main input
power supply of the board, since it is an always-on power supply. Connect
a Schottky diode (low forward voltage drop) between the output of the
regulator and the VCC_MCA pin. VIN_PRESENT must be tied to the output
of this 3.3V regulator. To allow coin-cell (low-power mode) applications,
the coin-cell/supercap must be connected to VCC_MCA again through a
Schottky diode. See Schematic: coin-cell/supercap connected to VCC_
MCA through Schottky diode.
Note In the ConnectCore 6UL reference designs (SBC PRO and SBC
Express) there's a 100 Ω series resistor between the coin-cell/supercap
and VCC_LICELL signal in the circuit above. Please remove this resistor. It
introduces a voltage drop in the transitory from normal operation to RTC
mode operation which could cause undesirable RTC behavior.
3V3_EXT is a dedicated 3.3V output power rail for powering external
circuitry of the carrier board. Do not connect any external power supply
to this line.
VCC_ENET is a 3.3V input power rail for supplying the ENET module of the
CPU. Digi recommends you feed this power domain directly from the
3V3_EXT power rail.
By default, leave the following power rails unconnected:
VCC_NAND (pad C12)
l
VDDA_ADC_3P3 (pad L3)
l
VDD_SNVS_3V3 (pad D12)
l
VCC_LICELL (pad B1)
l
3V3_INT (pad E3)
l
Although these signals are not used externally, it may be helpful to leave
them accessible for debugging (test points).
Naming and signal conventions
7