Changes To Table 9 - Analog Devices AN-877 Application Note

Application Note
Built-In Self Test (0x00E)
Register 0x00E configures and enables the built-in self test (BIST)
functions. The BIST is a user feature that provides a high degree
of confidence that the core process of the chip is performing as
intended. BIST provides a simple means of determining, in a
pass/fail manner, if the device is functioning. The results of the
BIST are available in 0x024 and 0x025, the multiple input status
register (MISR).
The BIST concept is a simple one. A PN sequence is fed to the
digital block of the converter. The output of the digital block is
added to an accumulator that was cleared at the start of the
BIST cycle. The accumulated result consists of the sum of all PN
sequences passed through the digital block. If the converter core
is functioning properly, it responds exactly the same every time
it is called. Therefore, the results should be consistent.
The results are placed in the MISR registers found at 0x024 and
0x025. The user can read these registers to determine if the
digital section of the chip is functioning properly. This is done
by comparing the values read with the values stored in the test
code. Because the digital back end has many different program-
ming options, there is no single value that represents a correct
response. Instead, once the user has determined the configuration,
the value from this register can be read on a working device to
determine the correct response. All working devices in the
specified configuration provide the same results. A different
result indicates a fault.
Bit 7 to Bit 3—Reserved
Bit 2—BIST Init
Bit 2 is the BIST Init bit. If low, the MISR is not cleared before
the BIST cycle is initiated. If this bit is high, the MISR is cleared
prior to the BIST cycle. This allows several tests to be cascaded
and the final results to be viewed rather than having to view
each individual test.
Bit 1 to Bit 0—BIST Mode
If the bit pattern is:
•
00, BIST mode is disabled and the chip operates normally.
•
01, BIST mode 1 is enabled.
When BIST Mode 1 is set, the internal digital stream of the
ADC is stimulated with a pseudorandom data stream and the
output is accumulated in the MISR registers (24h and 25h). Any
configuration settings that change data (offset or gain, for example)
or reformat data (offset binary or twos complement, for example)
affect the accumulation. Because the pseudorandom sequence is
predictable, the accumulated value is always the same for any
given configuration. This allows for a high degree of confidence
that the digital back end is fully functional. The integration period
is fixed at 256 encode cycles. After the BIST cycle is complete,
this bit is cleared, unless Bit 2 is clear.
Note that 10 and 11 are reserved for future BIST modes.
Analog Input (0x00F)
Register 0x00F configures the analog input.
Bit 7 to Bit 4—Bandwidth (Low-Pass)
Bit 7 to Bit 4 determine the corner frequency or the on-chip
low-pass filter. Note that 0000 is the default bandwidth, as
specified in the device data sheet. Alternate bandwidths are
defined with values 0001 through 1111. All options may not be
available. See the device data sheet for options available.
Table 9. Analog Input Bandwidth, Register 0x00F, Bits[7:4]
Bit 7 to Bit 4
0000
0001 through 1111
Bit 3—Reserved
Bit 2—Analog Disconnect
Bit 2 is set to disconnect the analog input from the remainder of
the ADC channel. When this bit is clear, the converter behaves
normally. However, if this bit is set, the converter continues to
operate, but with the analog input disconnected from the front
end of the circuit. This enables the user to determine the amount of
internal noise due to the converter, for applications that need
this information.
Bit 1—Common-Mode Input Enable
Bit 1 enables any common-mode circuitry associated with the
analog input of the ADC (see the device data sheet for additional
details of application and functionality).
Bit 0—Single Ended
Bit 0 is set if the input is single ended, for a device that otherwise
has a differential input, to enhance performance.
Offset Adjust (0x010)
Register 0x010 allows the offset of the device to be tweaked. The
purpose of this register is to provide sufficient offset to move
thermal noise off midscale. This is typically implemented as a
digital offset, and the range for this adjustment is found in the
device data sheet. The default of this register is 0x00 (midscale)
with representation using twos complement notation 0x7F is the
most positive offset adjustment, and 0x80 is the most negative
offset adjustment. An offset of positive 1 is represented as 0x01,
and a negative 1 is represented as 0xFF. The actual range of this
register varies by part (see the device data sheet).
Gain Adjust (0x011)
Register 0x011 allows the gain of the device to be adjusted. The
actual range and options vary by device (see the device data
sheet for additional details).
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AN-877
Bandwidth Mode
Default bandwidth.
Alternate bandwidth choices.