Format; Instruction Phase; Read/Write; Word Length - Analog Devices AN-877 Application Note

Application Note

FORMAT

The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of framing. Once the beginning of the
frame has been determined, timing is straightforward. The first
phase of the transfer is the instruction phase, which consists of
16 bits followed by data that can be of variable lengths in multiples
of 8 bits. If the device is configured with CSB tied low, framing
begins with the first rising edge of SCLK.

INSTRUCTION PHASE

The instruction phase is the first 16 bits transmitted. As shown
in Figure 4 and Figure 7, the instruction phase is divided into a
number of bit fields.
READ/ WRITE
The first bit in the stream is the read/write indicator bit (R/W).
When this bit is high, a read is being requested. At the com-
pletion of the instruction phase (the first 16 bits), the internal
state machine uses the information provided to decode the
internal address to be read. The direction of the SDIO line is
changed from input to output, and the appropriate number of
words defined by the word length are shifted out of the device
(see the Word Length section). If the device is equipped with an
SDO and the configuration register is appropriately set, the
SDO line is taken out of high impedance and data is passed out
the SDO pin instead of the SDIO pin. Once all data specified by
the word length has been shifted out, the state machine returns
to idle mode and awaits the next instruction phase.
CSB
CL DON'T CARE
SDIO
R/W W1 W0 A12 A11 A10 A9
DON'T CARE
Figure 7. Instruction Phase Bit Field
When the first bit in the data stream is low, a write phase is entered.
At the completion of the instruction phase, the internal state
machine uses the information provided to decode the internal
address to be written. All data after the instruction is shifted in the
SDIO pin and sent to the target addresses. Once all data specified
by the word length has been transferred, the state machine returns
to idle mode and awaits the next instruction phase.
In either read or write mode, the process continues until the word
length is reached or until the CSB line is lifted. If the end of
memory is reached (either 0x000 or 0x0FF), the rollover occurs
and the next address processed is 0x000, if the address is
incrementing, or 0x0FF, if the address is decrementing.

WORD LENGTH

W1 and W0 represent the number of data bytes to transfer for
either read or write. The value represented by W1:W0 + 1 is the
number of bytes to transfer. If the number of bytes to transfer is
three or less (00, 01, or 10), CSB can stall high on byte boundaries.
Stalling on a nonbyte boundary terminates the communications
cycle. If these bits are 11, data can be transferred until CSB
transitions high. CSB is not allowed to stall during the streaming
process. Once streaming has begun (defined as beyond the third
data byte), CSB is not allowed to return high until the operation is
complete. When CSB does go high, streaming is terminated, and
the next time CSB goes low, a new instruction cycle is initiated. If
CSB goes high on a non-8-bit boundary, the communications cycle
is terminated, and any incomplete bytes are lost. Completed data
bytes, however, are properly handled.
A8 A7 A6 A5 A4
16-BIT INSTRUCTION HEADER
Rev. B | Page 5 of 20
A3 A2 A1 A0
AN-877