Changes To Table 8 - Analog Devices AN-877 Application Note

AN-877
•
0101, the output is set to a PN23 sequence, based on ITU
0.150 using the equation x
0x003AFF. (See the device data sheet for applicable
deviations.)
•
0110, the output is set to a PN9, based on ITU 0.150 using
the equation x + x + 1. The seed value is 0x000092. (See
9 5
the device data sheet for applicable deviations.)
•
0111, the output words toggle between all 1s and 0s.
•
1000, the output is set to the user mode, controlled by Bit 7
and Bit 6. If the output is in user mode 0x08 and Bit 7 and
Bit 6 are set to 00, the pattern stored in the user pattern
memory is statically placed on the output. If set to 01, the
output toggles between User Pattern 1, stored in 0x019 and
0x01A, and User Pattern 2, stored in 0x01B and 0x01C. If
set to 10, User Pattern 1 is placed on the output for one
conversion cycle; then the output is set to all 0s. If set to 11,
Table 8. Output Test Modes, Register 0x00D
Output
Test
1
Mode Pattern
0000 Off
0001 Midscale short
0010 +FS short
0011 −FS short
0100 Checkerboard
0101 PN sequence long
0110 PN sequence short
0111 1/0 word toggle
1000 User input
1001 1/0 bit toggle
1010 1× sync
1011 1 bit high
1100 Mixed-frequency
1101 Reserved
1110 Reserved
1111 Chip specific
1 All devices may not support all modes. See the device data sheet for details.
Truncated from the right for lower resolutions.
2
See the device data sheet for applicable deviations.
3
+ x + 1. The seed value is
23 18
2
Word 1
Not applicable
1000000000000000
1111111111111111
0000000000000000
1010101010101010
Not applicable
Not applicable
1111111111111111
Register 19 to Register 1A
1010101010101010
0000000011111111
1000000000000000
101000110011 (12 bit)
1001100011 (10 bit)
10100001100111 (14 bit)
10100011 (8 bit)
Not applicable
Not applicable
Chip specific
User Pattern 1 and User Pattern 2, on the next encode
cycle, are placed on the output. Further conversion cycles
result in all 0s as determined by the output data format.
•
1001, the output is placed in a 1/0 bit toggle mode for serial
output testing. This forces an alternating 1/0 transition on
the serial output stream.
•
1010, the first half of the bits are set to 0 and the last half of
the bits are set to 1. The cycle repeats for the next word
frame (see Table 8 for details).
•
1011, the first bit of the serial word is set high and the
following bits in the word are set low.
•
1100, the serial words shown in Table 8 are shifted.
Bit Mode 1101 and Bit Mode 1110 are reserved for future use.
Bit Mode 1111 is reserved for chip-specific test requirements.
2
Word 2
Not applicable
Not applicable
Not applicable
Not applicable
0101010101010101
Not applicable
Not applicable
0000000000000000
Register 1B to Register 1C
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Chip specific
Rev. B | Page 12 of 20
Application Note
Subject to
Data Format
Select Notes
Yes
Yes Offset binary code shown
Yes Offset binary code shown
Yes Offset binary code shown
No
Yes PN23 3
ITU 0.150
x + x + 1
23 18
Yes PN9 3
ITU 0.150
x 9 + x 5 + 1
No
No
No Useful in serial output mode
No Lower resolution truncates both
a leading and a trailing digit
No Useful in serial output mode
No Useful in serial output mode
Not applicable Not applicable
Not applicable Not applicable
Chip specific Chip specific