Analog Devices AN-877 Application Note page 19

Application Note
Address , Register Bit 7 (MSB)
1
0: Level Option 0
14, OUTPUT_MODE
1: Level Option 1
2: Level Option 2
3: Level Option 3
15, Output driver termination; Bits[7:4]
OUTPUT_ADJUST
Output
16, OUTPUT_PHASE
polarity
17, OUTPUT_DELAY Enable
V select
18, VREF
REF
0: primary (0)
1: secondary (1)
2: Option 2
3: Option 3
19,
B7
USER_PATT1_LSB
1A,
B15
USER_PATT1_MSB
1B,
B7
USER_PATT2_LSB
1C,
B15
USER_PATT2_MSB
1D,
B7
USER_PATT3_LSB
1E,
B15
USER_PATT3_MSB
1F,
B7
USER_PATT4_LSB
20,
B15
USER_PATT4_MSB
21,
LSB first
SERIAL_CONTROL
22,
SERIAL_CH_STAT
24, MISR_LSB B7
25, MISR_MSB B15
2A, FEATURES
2B, HIGH_PASS
2C, AIN
2D, CROSS_POINT
Enable HW
FF, DEVICE_UPDATE
transfer
Hexadecimal.
1
2 Not supported on most devices.
Bit 6 Bit 5 Bit 4
Output Output
mux enable
enable
(interleave)
DLL
enable
6-bit internal V
B6 B5 B4
B14 B13 B12
B6 B5 B4
B14 B13 B12
B6 B5 B4
B14 B13 B12
B6 B5 B4
B14 B13 B12
B6 B5 B4
B14 B13 B12
Tune
Bit 3 Bit 2 Bit 1
DDR Output
enable invert 1: Twos complement
Output driver current; Bits[3:0]
Output clock phase adjust; Bits[3:0]
6-bit output delay; Bits[5:0]
adjustment; Bits[5:0]
REF
B3 B2 B1
B11 B10 B9
B3 B2 B1
B11 B10 B9
B3 B2 B1
B11 B10 B9
B3 B2 B1
B11 B10 B9
PLL 000: normal bit stream
optimize 001: 8 bits
010: 10 bits
011: 12 bits
100: 14 bits
101: 16 bits
Ch output
reset
B3 B2 B1
B11 B10 B9
OVR
alternate
pin
Corner frequency
000: dc
000 through 111: Alternate corner
frequencies
Rev. B | Page 19 of 20
Default
1
Value
Bit 0 (LSB)
0: Offset binary Device
specific
2: Gray code
3: Reserved
Device
specific
00h
00h
20h
B0 00h
B8 00h
B0 00h
B8 00h
B0 00h
B8 00h
B0 00h
B8 00h
00h
Ch
00h
power-
down
B0 00h
B8 00h
OVR output
00h
enable
00h
Input
00h
impedance
00h
SW transfer 00h
AN-877
Comments
Configures the outputs
and the format of the data.
Determines LVDS or other
output properties.
Primarily functions to set
the LVDS span and
common-mode levels in
place of an external
resistor.
On devices that utilize
clock divide, determines
which phase of the divider
output is used to supply
the output clock. Internal
latching is unaffected.
This sets the fine output
delay of the output clock
but does not change
internal timing.
Select and/or adjust the V .
REF
User-Defined Pattern 1 LSB.
User-Defined Pattern 1 MSB.
User-Defined Pattern 2 LSB.
User-Defined Pattern 2 MSB.
User-Defined Pattern 3 LSB.
User-Defined Pattern 3 MSB.
User-Defined Pattern 4 LSB.
User-Defined Pattern 4 MSB.
Serial stream control.
Default causes MSB first
and the native bit stream.
Used to power down
individual sections of a
converter (local).
Least significant byte of
MISR (read-only).
Most significant byte of
MISR (read-only).
Auxiliary feature set
control.
High-pass filter control.
Analog input control.
Analog input cross point
switch.
Synchronously transfers
data from the master shift
register to the slave.