Changes To Table 3 Caption; Chip Programming; Configuration Register (0 000); Transfer Register (Master-Slave Latching) (0X0Ff) - Analog Devices AN-877 Application Note

AN-877

CHIP PROGRAMMING

The SPI port is the mechanism for configuring the converter. In
addition, a structured register space is defined for programming
the device. This structure is divided into addresses pointed to by
the address in the instruction phase of the data transfer. Each
address is divided into 8-bit bytes. Each byte can be further divided
down fields, which are documented in the following sections.
There are three types of registers: the configuration register, the
transfer register, and the program register.
CONFIGURATION REGISTER (0
The configuration register is located at Address 0x000. This register
is used to configure the serial interface, and it contains only four
active bits in the upper nibble. The lower nibble is not connected
and is held in reserve. Actively mirroring the data between the
upper and lower nibble is recommended. By doing so, any loss
of synchronization and directional information can be easily
restored by writing to Address 0x000. Additionally, it enables
the chip to be soft reset and configured in a known state, regardless
of which direction data is currently being shifted. This ensures
positive attention by the device if a fault condition occurs.
Bit 7—SDO Active
Bit 7 must be mirrored by the user in Bit 0. This bit is responsible
for activating SDO on devices that include this pin. If the device
does not include an SDO pin, setting this bit has no effect. If this bit
is cleared, then SDO is inactive and read data is routed to the
SDIO pin. If this bit is set, read data is placed on the SDO pin, if
so equipped. The default for this bit is low, making SDO inactive.
Bit 6—LSB First
Bit 6 must be mirrored by the user in Bit 1. This bit is responsible
for the order of information being sent and received. If this bit
is clear, then data is processed MSB first. If this bit is set, then
data is processed LSB first. In addition to the order of data shifting,
Bit 6 controls the direction of auto-incrementing of the internal
address pointer. If this bit is clear, that is, MSB-first mode, the
internal address counter is decremented for each new datum
processed. Contrarily, if this bit is set for LSB-first mode, the
internal address counter is incremented for each new datum
processed. The default for this bit is cleared, resulting in MSB-
first operation.
Bit 5—Soft Reset Control
Bit 5 must be mirrored by the user in Bit 2. This bit is the soft
reset control. The default for this bit is clear; however, when set
high by the user, a chip soft reset is initiated. The soft reset returns
all default values to the memory map registers except the
configuration register (0x000). Values that have no defaults
remain in the state last programmed by the user. Once the soft
reset is processed, this bit is cleared, indicating that the reset
process is complete.
000)
X
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Bit 4—Reserved
Bit 4 must be mirrored by the user in Bit 3. This bit defaults to 1
and cannot be changed.
Table 3. Configuration Register 0x000
Bit Name Description
Bit 7 SDO When set, causes SDO to
become active (if present).
active
When clear, the SDO pin
remains in tristate and all
read data is routed to the
SDIO pin.
Bit 6 LSB first When set, causes input
and output data to be
oriented as LSB first and
addressing increments.
When this bit is clear, data
is oriented as MSB first and
addressing decrements.
Bit 5 Soft reset When set, the chip enters
a soft reset mode,
restoring any default
values to internal registers.
Registers with no default
are not changed. Once this
is complete, the state
machine clears this bit.
Bit 4 Reserved Default cannot be changed.
TRANSFER REGISTER (MASTER-SLAVE LATCHING)
(0x0FF)
It is desirable for many of the registers in the register map to be
buffered with master and slave latches. Buffering enhances the
ability to synchronize multiple devices in a system and aids in
writing configurations that may be dependent on values written
in other parts of memory. Depending on the design, some registers
may be buffered in this manner. Some registers are never buffered,
such as 0x000, 0x004, 0x005, and 0x0FF, because they require
immediate response for program and control purposes. (Consult
the device data sheet to determine which registers are buffered.)
Regardless of buffering, the SPI port is responsible for placing
information in the registers. However, for registers that are
buffered, a transfer must be initiated to move the data to the
slave registers. There are two defined mechanisms that cause
the data to be transferred from the master register to the slave
register. Unbuffered latches take effect immediately once
received by the SPI state machine.
On some devices, the transfer bit may be located higher in
memory if the device supports unique device-specific features.
In these cases, the functionality of the transfer bit is the same;
only the location is different. See the device data sheet for details.
Application Note
Default
Clear. SDIO is
used for both
input and output.
Clear. MSB first
and decrementing
addressing.
Clear. On-chip
power up, any
register with a
default is set.
Set.