Chip Id (0X001); Chip Grade (0X002); Device Indexing (0X004 And 0X005) - Analog Devices AN-877 Application Note

Application Note
Bit 0—Software Transfer
A software transfer is initiated by setting Bit 0 of this register
as shown in Figure 10. When the state machine recognizes that
this bit is set, it generates an internal transfer signal that moves
data from the master register to the slave register. When complete,
the state machine clears this bit, allowing the user to determine
if the transfer has occurred. It is recommended that all other
registers be configured as desired before initiating a transfer.
Once the masters have been set, the last instruction should
cause the data to be transferred. Data are maintained in the
masters indefinitely, as long as power is applied. Therefore, it
is possible to set up many chips independently and initiate a
transfer to occur simultaneously across multiple chips by
broadcasting the transfer command to all chips at the same
time. Broadcasting can be achieved by bringing all CSB lines
low at the same time, which sends the same data to all chips at
once.
Bit 7—Enable Hardware Transfer
Not all devices support a hardware transfer mechanism (see the
device data sheet to determine applicability). Bit 7 of this register is
assigned the purpose of enabling hardware synchronization. If Bit 7
is clear, the default software synchronization is enabled. If this bit is
set, transfer control is passed to the specified external pin (see
Figure 13).

CHIP ID (0x001)

Register 0x001 is the chip ID register, a read-only register that
returns the unique chip identifier that is coded during the
design process, which typically indicates the child ID or grade
of the device. This serves to identify which die is used in the
package when multiple grades or options exist (see the device
data sheet to determine the correct ID).

CHIP GRADE (0x002)

Register 0x002 is the chip grade register. This optional register
may or may not contain end-user device information (see the
device data sheet to determine if this register is supported and
what the values mean).

DEVICE INDEXING (0x004 AND 0x005)

Register 0x004 and Register 0x005 are used for indexing individual
converters on the same die. Register 0x005 references the lower-
order devices ADC0 through ADC3, while 0x004 references the
upper order devices ADC4 through ADC7. If there is only one
ADC in the package, this register is not used. However, if there
are several ADCs, this register must be used to indicate which
device is being written to or read from. During a write process,
more than one device at a time can be written by setting multiple
bits in these registers that correspond to the
ADC channels to be written high. During a read process, only
one bit at a time is recommended to be set high to prevent
confusion over which ADC is currently placed on the read bus.
Circuitry on-chip prevents bus contention, but the channel
selected for readback is not known unless only one ADC at a
time is enabled.
Bit 7 to Bit 4—Auxiliary Devices
The upper nibble is used to enable other devices that may be
on-chip, such as clock generators or secondary converters.
Bit 3 to Bit 0—Main Converters
The lower nibble is used to enable up to four ADCs. Because
there are two registers, a total of eight ADCs can be accessed.
Writing
Because the ADC enables are not decoded, it is possible to write
to multiple devices at one time. To accomplish this, set Bit 0
through Bit 3 to enable writing to the selected device. It is possible
to write to a subset of these registers by setting only those bits
that correspond to the desired target converters. If both 0x004
and 0x005 are used, bit fields in both registers can be set to write to
any or all of the ADCs (0 through 7) as well as any or all of the
auxiliary devices.
Reading
When reading from devices, only one device at a time can be
placed on the serial bus. No damage results if multiple devices
are enabled, but the results may be indeterminate. Therefore,
care must be taken to enable only one device at a time during
readback operations.
INTERNAL TRANSFER
SIGNAL (MASTER-SLAVE)
CSB
SCLK
A1 A0
SDIO
MSB-FIRST WRITE INSTRUCTION
CSB
SCLK
W1 R/W
SDIO
LSB-FIRST WRITE INSTRUCTION
Rev. B | Page 9 of 20
D7 D6 D5 D4 D3 D2 D1
DATA
D0 D1 D2 D3 D4 D5 D6
DATA
Figure 12. Internal Latching Sequence
AN-877
DON'T CARE
DON'T CARE
D0 DON'T CARE
DON'T CARE
DON'T CARE
D7 DON'T CARE