Streaming; Changes To Table 2 Caption; Address Bits - Analog Devices AN-877 Application Note

AN-877
Table 2. Word Length Settings
[W1:W0]
Setting Action
00 1 byte of data can be transferred.
01 2 bytes of data can be transferred.
10 3 bytes of data can be transferred.
4 or more bytes of data can be
11
transferred. CSB must be held low for
entire sequence; otherwise, the cycle is
terminated, and an instruction cycle is
anticipated when CSB returns low.
If the value represented by W0 and W1 is 0, one byte of data is
transferred. If the value represented by W0 and W1 is 1, two
bytes of data are transferred. If the value represented by W0 and
W1 is 2, then three bytes of data are transferred. Following
completion of the data transfer, the state machine returns to idle
state, awaiting the next instruction phase.

STREAMING

If the value represented by W0 and W1 is 3, data is constantly
streamed to the device. As long as CSB remains low, the part
continues to accept new data, starting with the initial address
and continuing to the next address with each new word
received. It is recommended that streaming not be combined
with the CSB line physically tied low, because streaming can
only be terminated by lifting the CSB line high. If streaming is
used with CSB tied low, the first instruction used is carried out
indefinitely. This means that once a write (or read) cycle is
entered, data may not be read (or written) from the device.
Similarly, the starting address is continually and automatically
incremented/decremented, according to the mode, with no
chance to directly change the address of the state machine. (The
address generator continues to wrap around the terminal
addresses in a predictable manner.) This may not be a problem
if the user only wants to program the device with no possibility
of reading internal registers. It is recommended that users who tie
CSB
SCLK DON'T CARE
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDIO DON'T CARE
MSB-FIRST 16-BIT INSTRUCTION, 2 BYTES DATA
CSB
SCLK DON'T CARE
DON'T CARE
SDIO A0 A1 A2 A3 A4 A5 A6 A7
LSB-FIRST 16-BIT INSTRUCTION, 2 BYTES DATA
CSB
Stalling
Optional
Optional
Optional
No
16-BIT INSTRUCTION HEADER
A8 A9 A10 A11 A12 W0
16-BIT INSTRUCTION HEADER
Figure 8. MSB-First and LSB-First Instruction and Data Phases
Rev. B | Page 6 of 20
the CSB line low transfer data in 1-, 2-, or 3-byte blocks, unless
they are certain that they do not wish to read data from the
internal registers. Although it is not required, it is recommended
that users maintain control over the CSB line so the streaming
process can be interrupted and the state machine can be reset to
the idle state.

ADDRESS BITS

The remaining 13 bits represent the starting address of the data
sent. If more than one word is being sent, sequential addressing
is used, starting with the one specified, and it either increments
or decrements based on the mode setting.
Data Phase
Data follows the instruction phase. The amount of data sent is
determined by the word length (Bit W0 and Bit W1). This can
be one or more bytes of data. All data is composed of 8-bit
words. If the state machine detects incomplete data being
transmitted, the state machine resets and enters an idle state,
awaiting a new instruction to be initiated by the next falling
edge of the CSB line. If CSB is physically tied low, fault
correction is not possible unless the device includes a chip reset
function. (See the individual device data sheets for more detail.)
Bit Order
Data can be sent in either MSB-first mode or LSB-first mode
(see the Configuration Register (0X000) section). On power up,
MSB-first mode is the default. This can be changed by program-
ming the configuration register. In MSB-first mode, the serial
exchange starts with the highest-order bit and ends with the
least significant bit (LSB). In LSB-first mode, the order is reversed.
The instruction is 16 bits long, consisting of 2 bytes, as described
earlier. In MSB-first mode, the bit order is highest-order bit to
lowest-order bit. In LSB-first mode, the entire 16 bits are reversed,
as shown in Figure 8.
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER (N) DATA
W1 R/W D0 D1 D2 D3 D4 D5 D6 D7
REGISTER (N) DATA
Application Note
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER (N–1) DATA
D0 D1 D2 D3 D4 D5 D6 D7
REGISTER (N–1) DATA
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE