Changes To Table 14; Control Register - Analog Devices AN-877 Application Note

AN-877

CONTROL REGISTER

Table 14. Control Register Map
Address 1 , Register Bit 7 (MSB)
00,
SDO active
2
CHIP_PORT_CONFIG
01, CHIP_ID
02, CHIP_GRADE
04,
AUX 7
DEVICE_INDEX_B
05,
AUX 3
DEVICE_INDEX_A
External
08, MODES
power-down
enable
09, CLOCK Reserved for additional clock input support
0A, PLL_CONTROL PLL locked
0B, CLOCK_DIVIDE
0C, ENHANCE Reserved
User test mode
0D, TEST_IO
00: single
01: alternate
10: single once
11: alternate once
0E, TEST_BIST
0F, ADC_INPUT
Bits[1:15]: alternate corner frequencies
(See device data sheet for details)
10, OFFSET
11, GAIN
Bit 6 Bit 5 Bit 4
Should
LSB first Soft reset
be set.
Do not
clear.
8-bit chip ID; Bits[7:0]
8-bit child ID
AUX 6 AUX 5 AUX 4
AUX 2 AUX 1 AUX 0
External power-down
mode
00: full power-down
01: standby
10: normal mode
(output disabled)
11: normal mode
(output enabled)
PLL auto
Clock divider; Bits[7:0]
Reserved Reserved
Reset PN Reset PN
long gen short gen
Low-pass filter bandwidth
0: default
8-bit device offset adjustment; Bits[7:0]
8-bit device gain adjustment; Bits[7:0]
Bit 3 Bit 2 Bit 1
ADC 7 ADC 6 ADC 5
ADC 3 ADC 2 ADC 1
Function Internal power-down mode
bypass 0: chip run
1: full power-down
2: standby
3: reset
4: ADC power-down
5: analog front-end power-down
6: reserved
7: reserved
PLL enable Clock boost
PLL multiplier; Bits[5:0]
Chop enable
0: off
1: Mode 1
2: Reserved
3: Reserved
Output test mode
0: off
1: midscale short
2: +FS short
3: −FS short
4: checkerboard output
5: PN23 sequence
6: PN9
7: 1/0 word toggle
8: User input
9: 1/0 bit toggle
10: 1× sync
11: 1 bit high
12: mixed-bit frequency (format
determined by OUTPUT_MODE)
BIST init Reserved
Analog Common-
disconnect mode
input
enable
Rev. B | Page 18 of 20
Application Note
Default
1
Value
Bit 0 (LSB) Comments
The nibbles should be
18h
mirrored by the user so
that LSB-first or MSB-first
mode registers correctly
regardless of shift mode.
Read Default is unique chip ID,
only different for each device.
This is a read-only register.
(See device data sheet for
more details.)
Read Read only. Child ID used
only to differentiate graded
devices. (See device data
sheet for more details.)
Bits are set to determine
ADC 4 FFh
which device on -chip
receives the next write
command. The default will
be all devices on-chip.
Bits are set to determine
ADC 0 FFh
which device on-chip
receives the next write
command. The default is
all devices on-chip.
Determines various
00h
generic modes of chip
operation.
Duty cycle
01h
stabilize
Configures on-chip PLL by
00h
enabling and setting
multiplier. MSB is set
when the PLL is locked.
The divide ratio is the
00h
value plus 1.
Shuffle mode Shuffle mode determines
0: off how shuffling is
1: Mode 1 performed. Chopping
2: Reserved determines how the input
3: Reserved is processed to improve
noise near dc.
When set, the test data is
00h
placed on the output pins
in place of normal data.
BIST enable 00h BIST mode configuration
Single
00h
ended
80h Device offset trim
00h Device gain trim