Serial Data Out (Sdo) - Analog Devices AN-877 Application Note

AN-877

SERIAL DATA OUT (SDO)

To determine if a device supports the SDO pin, refer to the device
data sheet. If SDO is present, it is in a high impedance state, unless
data is actively being shifted on this pin to allow tying multiple
devices together at the receiving end. Additionally, data is shifted
out on the first falling edge of SCLK after the instruction phase is
complete. When data is returned to the controller, the information
is placed in the output shifters, within the time period between the
last rising edge of SCLK associated with the instruction phase and
the immediately next falling edge. This can be nominally 20 ns
when operating at 25 MHz.
CSB
SPI SCLK
CONTROLLER
SDO
SDI
Figure 3. 3-Wire Control
t
S
CSB
DON'T CARE
SCLK
SDIO
DON'T CARE
CSB
SCLK DON'T CARE
DON'T CARE R/W W1 W0 A12 A11 A10 A9
SDIO
16-BIT INSTRUCTION HEADER
CSB
SCLK DON'T CARE
DON'T CARE R/W W1 W0 A11 A11 A10 A9
SDIO
16-BIT INSTRUCTION HEADER
SCLK
OUTPUT DRIVER OFF
CSB
CONVERTER
SCLK
INTERFACE
SDIO
SDO
HIGH-Z WHEN
NOT USED OR
INACTIVE
t t
DS
HI
t
DH
R/W W1 W0 A12 A11
Figure 4. Setup and Hold Timing Measurements
A8 A7 A6 A5 A4 A3 A2 A1 A0
MSB-FIRST 16-BIT INSTRUCTION, 3 BYTES DATA WITH STALLING
Figure 5. Most Significant Bit (MSB)-First Instruction and Data with Stalling
A8 A7 A6 A5 A4 A3 A2 A1 A0
REGISTER (N) DATA
MSB FIRST 16-BIT READ INSTRUCTION, 4 BYTES DATA 4-WIRE
OUTPUT DRIVER ON
t
EN_SDIO
Figure 6. Typical SDIO Output Enable and Disable Timing
Table 1. Serial Timing Specifications
Symbol
t
DS
t
DH
t
CLK
t
S
t
H
t
HI
t
LO
t
EN_SDIO
t
DIS_SDIO
1 See device data sheet for minimum and maximum ratings.
t
CLK
t
LO
A10 A9 A8 A7 D5
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER (N) DATA
DRIVEN OUTPUT DATA STREAM
REGISTER (N – 1) DATA
Rev. B | Page 4 of 20
Application Note
1
Description
Setup time between data and rising edge of SCLK.
Hold time between data and rising edge of SCLK.
Period of the clock.
Setup time between CSB and SCLK.
Hold time between CSB and SCLK.
Minimum period that SCLK needs to be in a logic
high state.
Minimum period that SCLK needs to be in a logic
low state.
Minimum time it takes the SDIO pin to switch
between an input and an output relative to SCLK
falling edge.
Minimum time it takes the SDIO pin to switch
between an output and an input, relative to SCLK
rising edge.
D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7
REGISTER (N–1) DATA
REGISTER (N – 2) DATA REGISTER (N – 3) DATA
SCLK
OUTPUT DRIVER ON
t
DIS_SDIO
t
H
DON'T CARE
DON'T CARE
DON'T CARE
D6 D5 D4 D3 D2 D1 D0 DON'T CARE
REGISTER (N–2) DATA
R/W W1
. . .
OUTPUT DRIVER OFF