Timing Diagram; 2/06-Rev. 0 To Rev. A. Changes To Table 1 - Analog Devices ADT7473 Manual

ADT7473/ADT7473-1
Parameter
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Low Current, I
IL
Input Capacitance, C
IN
SERIAL BUS TIMING
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
r
SCL, SDA Fall Time, t
f
Data Setup Time, t
SU; DAT
Detect Clock Low Timeout, t
1
All voltages are measured with respect to GND, unless otherwise noted. Typicals are at T
high voltages up to V , even whenthe device is operating down to V
MAX
for a rising edge.

TIMING DIAGRAM

Serial management bus (SMBus) timing specifications are guaranteed by design and are not production tested.
SCL
t
HD; STA
SDA
t
BUF
P S
Min
2.0
−0.3
10
4.7
4.7
4.0
250
15
TIMEOUT
t t
R F
t
LOW
t
HIGH
t
HD; DAT
Figure 2. Serial Bus Timing Diagram
Typ Max
3.6
0.8
0.5
0.75 × V
CC
0.4
±1
±1
5
400
50
50
1,000
300
35
= 25°C and represent most likely parametric norm. Logic inputs accept input
A
. Timing specifications are tested at logic levels of V
MIN
t
SU; STA
t
SU; DAT
S
Rev. C | Page 4 of 72
Unit Test Conditions/Comments
V
V Maximum input voltage
V
V Minimum input voltage
V p-p
V
V
μA V = V
IN CC
μA V = 0
IN
pF
See Figure 2
kHz
ns
μs
μs
μs
ns
μs
ns
ms Can be optionally disabled
= 0.8 V for a falling edge and V
IL
t
HD; STA
t
SU; STO
= 2.0 V
IH
P