Changes To Table 6 And Table 7; Added Table 6; Added Pll Control (0X00A) Section - Analog Devices AN-877 Application Note

Application Note
PLL Control (0x00A)
Register 0x00A is used to enable and control an on-chip PLL
that may be used to generate a sample clock.
Bit 7—PLL Locked
This bit is controlled by the internal hardware and is set when
the PLL is locked. If this bit is clear, the chip has not yet locked.
Bit 6—PLL Auto
When this bit is set, the PLL automatically chooses the most
appropriate PLL setting for the specified divider.
Bit 5 to Bit 0
Set to the PLL divide ratio plus 1.
Clock Divider (0x00B)
Register 0x00B is used to divide the applied clock to a lower rate
for the encode. If set to all 0s, the divider is bypassed.
Otherwise, the divide ratio is the value in the register plus 1.
Enhancement Modes (0x00C)
Register 0x00C controls enhancement modes.
Bit 7 to Bit 4—Reserved
Bit 3 to Bit 2—Chop Enable
Chopping is used to improve noise performance at or near dc.
If Bit 3 to Bit 2 are set to:
•
00, internal chopping is disabled.
•
01, Chopping Mode 1 is enabled.
•
10, Chopping Mode 2 is enabled.
•
11, Chopping Mode 3 is enabled.
(See the device data sheet for details.)
Table 6. Enhancement Modes, Register 0x00C, Bits[3:2]
Bit 3 to Bit 2 Chopping Modes
00 No chopping
01 Enable Chopping Mode 1
10 Enable Chopping Mode 2
11 Enable Chopping Mode 3
Bit 1 to Bit 0—Shuffle Mode
Shuffling is used to improve the linearity of the ADC transfer
function.
If Bit 1 to Bit 0 are set to:
•
00, internal shuffling is disabled.
•
01, Shuffling Mode 1 is enabled.
•
10, Shuffling Mode 2 is enabled.
•
11, Shuffling Mode 3 is enabled.
Table 7. Enhancement Modes, Register 0x00C, Bits[1:0]
Bit 1 to Bit 0
00
01
10
11
Output Test Modes (0x00D)
Register 0x00D enables available test modes (see the device data
sheet to determine what modes are supported). The default
setting for this register is 0x00; however, when this register is set
to one of the documented settings, the ADC data is replaced
with test mode data. For Test Modes numbered 1, 2, 3, 5, and 6,
the output format is determined by the setting of Register 0x014.
All other output patterns provide logical output sequences and
are not affected by the output format setting of Register 0x014.
Bit 7 to Bit 6—Sequencing
These bits are used in conjunction with Test Mode 8 defined by
Bit 3 to Bit 0.
If these bits are set to:
•
00, then the test pattern stored in 0x019 and 0x01A is
statically placed on the output.
•
01, the pattern alternates between the pattern stored in
User Pattern 1 (0x019 and 0x01A) and User Pattern 2
(0x01B and 0x01C).
•
10, User Pattern 1 is placed on the output for one
conversion cycle. Then the output is set to all 0s.
•
11, User Pattern 1 is placed on the output followed by User
Pattern 2 on the next encode cycle. Further conversion
cycles result in all 0s as determined by the output data
format.
Bit 5—PN23 Reset
Bit 5 controls the reset long PN sequence (PN23). While this bit
is set, the PN sequence is held in reset. When this bit is cleared,
the PN sequence resumes from the seed value. The seed value is
0x003AFF.
Bit 4—PN9 Reset
Bit 4 controls the reset short PN sequence (PN9). While this bit
is set, the PN sequence is held in reset. When this bit is cleared,
the PN sequence resumes from the seed value. The seed value is
0x000092.
Bit 3 to Bit 0—Test Modes
When these bits are set to:
•
0000, the device functions as a normal ADC.
•
0001, the output is set to digital midscale.
•
0010, the output is set to +FS.
•
0011, the output is set to −FS.
•
0100, the output is set to an alternating checkerboard
pattern.
Rev. B | Page 11 of 20
AN-877
Shuffle Modes
No shuffling
Enable Shuffle Mode 1
Enable Shuffle Mode 2
Enable Shuffle Mode 3