Configuration Switch (S1) And Jumpers (W1 And W3); Table 7: Configuration Settings - Intel CHIPS HiQVideo Series User Manual

4.1 Configuration Switch (S1) and Jumpers (W1 and W3)

The ABHiQV provides one on-board Dip Switch S1 and two jumpers W1 and W2 for various configuration
settings.
There are three configuration bits (CFG7,4,1) which are latched from AA7,4,1 on reset. CFG7,4,1 are writ-
ten into the HiQVideo™ controller extended register XR70[7:0].
Four additional configuration bits, CGF14:11 are latched into XR71[6:3] from MAD[6:3] on reset. The soft-
ware reserves these configuration bits for input of panel IDs. They correspond to DIP switch S1 positions
5:2 on the ABHiQV daughtercard.
All CFG pins have internal weak pull up and may be pulled down by 4.7k resistors on the daughtercard if
the DIP switches are set to ON. Table 7 summarizes all the CFG bits and corresponding DIP switches and
jumpers W1 and W3.

Table 7: Configuration Settings

Bits Latched
From
CFG0 AA0 Reserved
CFG1 AA1
CFG2 AA2 Reserved
CFG3 AA3 Reserved
CFG4 AA4
CFG5 AA5 Reserved
CFG6 AA6 Reserved
CFG7 AA7
CFG8 AA8 Reserved
CFG10 MA 2 Reserved
CFG11 MA 3
CFG12 MA 4
CFG13 MA 5
CFG14 MA 6
Refer to the applicable databook for additional configuration options.
&+,36
®
ABHiQV (Fab Rev. C)
User's Guide
Name Purpose
PCI VGA I/O Decoding Enable/
Disable on PCI bus
Ext. CLK External OSC for MCLK
and DCLK
ACTI/ENABKL
CLK-TST Internal clock test mode
disable
PID0 Panel Type
PID1 Panel Type
PID2 Panel Type
PID3 Panel Type
Subject to Change Without Notice
Daughtercard
XR Bits DIP Switch Posi-
tion and Defaults
XR70[0]
XR70[1] S1[6]: open
XR70[2]
XR70[3]
XR70[4] W1: open
XR70[5]
XR70[6] W3: open
XR70[7] S1[7]: open
XR71[0]
XR71[2]
XR71[3] S1[5]: open
XR71[4] S1[4]: open
XR71[5] S1[3]: open
XR71[6] S1[2]: open
Revision 1.1
11
7/15/98