Page 3
Revision History Date Version Description 4/17/2017 1.00E Initial version published. Update configuration mode and value of different supported device; 5/31/2017 1.01E Update RECONFIG N notes during programming built-in Flash. 10/13/2017 1.02E Description of reusing pins updated. 3/16/2018 1.03E Add GW1NS programming and configuration description.
Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Supported Products ......................1 1.3 Related Documents ......................1 1.4 Abbreviations and Terminology ................... 2 1.5 Support and Feedback .......................
1.1 Purpose This guide mainly introduces general features and functions on programming and configuration of GW1N (R), GW1NS, and GW2A (R) series of FPGA products. It helps users to use Gowin FPGA products to their full potential. 1.2 Supported Products The information in the guide applies to all Gowin FPGA products.
Cyclic Redundancy Check Cyclic Redundancy Check 1.5 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail: support@gowinsemi.com...
This chapter presents an overview of the terms that are commonly used when programming and configuring Gowin FPGA products. Familiarizing yourself with the glossary items listed below will help you to make the most out of the Gowin FPGA products. Table 2-1 Glossary Glossary...
Page 11
Each series of devices has a different number. Write to identify the FPGA device through the USER CODE Gowin programming software, which can be up to 32-bit. A special design for protecting the security of the Gowin FPGA product configuration data. After...
3Configuration Mode and Power-on Requirements 3.1GW1N(R/S) series of FPGA Products Configuration Mode and Power-on Requirements 3.1 GW1N(R/S) series of FPGA Products Besides JTAG, the GW1N(R/S) series of FPGA products also support GOWINSEMI's own configuration mode: GowinCONFIG. GowinCONFIG configuration modes that are available and supported for each device depend on the device model and package.
The GW1N(R) series of FPGA products SSPI are configured by hardware processor via SPI interface. As master, the GW1N series of FPGA products are configured by reading data MSPI from the external Flash (or another device) through the SPI interface...
3Configuration Mode and Power-on Requirements 3.2GW2A(R) series of FPGA Products Table3-2 Recommended Power Supply Voltage Name Description Min. Max. LV: Core Power 1.14V 1.26V UV: Core Power 1.71V 3.465V I/O Bank Power 1.14V 3.6V Auxiliary Power 2.3V 3.465V 3.2 GW2A(R) series of FPGA Products Besides JTAG, the GW2A(R) series of FPGA products also support GOWINSEMI's own configuration mode: GowinCONFIG.
3Configuration Mode and Power-on Requirements 3.2GW2A(R) series of FPGA Products 3.2.2 Power Supply Voltage The GW2A(R) series of FPGA products contain one power-on reset module. The recommended power supply voltage is as shown in Table3-2. The device remains in a reset state until the power supply conditions are met.
4.1.1 Configuration Pin List and Reuse Options Table 4-1 contains a list of all the pins of that are required to configure Gowin FPGA products together with the details of the shared pins in each configuration mode and chip packaging process.
GW2A (R) series of FPGA Products Configuration Guide for configuration modes supported for different devices; Please refer to 5Configuration Mode for the definition of each pin in each respective configuration mode. 4.1.2 Pin Multiplexing To maximize the utilization of the I/O, Gowin FPGA product support set UG290-1.04EUG290-1.04E 10(50)
4Configuration Pin 4.1Configuration Pin List and Reuse Options the configuration pins to regular I/O pins. Before any configuration operation is performed on the products in the FPGA series, the pins associated with the configuration are used as configuration pins by default. After successful configuration, the device enters into user mode and redistributes the pin functions according to the reuse options selected by the user.
4Configuration Pin 4.2Pin Function and Application To configure pin reuse via the Gowin software: 1. Open the corresponding project in Gowin software; 2. Select “Project > Configuration > Dual Purpose Pin” from the menu options, as shown in Figure 4-1;...
Page 20
RECONFIG_N, the device turns into the MODE corresponding state in accordance with the GowinCONFIG MODE value, each MODE value of the Gowin series of FPGA products that corresponds to the configuration MODE is slightly different. Please refer to the corresponding device UG290-1.04EUG290-1.04E...
Page 21
As a configuration pin, DIN is an input pin with internal weak pull-up. If the JTAG pin is set as a GPIO in the Gowin software, the JTAG pin can become GPIO after being powered up and successfully configured. The JTAG pin can be recovered by pulling down JTAGSEL_N.
Page 22
MCLK oscillator. The MCLK frequency values can be modified through the Gowin software interface, as shown in Figure 4-2. Open Gowin software engineering, select "Project > Configuration" from the menu options, click "BitStream" and select the MCLK frequency values in the "Download Speed"...
Page 23
4Configuration Pin 4.2Pin Function and Application Pin Name Functional Description mode. As a GPIO, it can be used as an input or output type. As a configuration pin, DOUT is an output pin. Serial data output pin in MSPI configuration mode. As a GPIO, it can be used as an input or output type.
5Configuration Mode 4.2Pin Function and Application Configuration Mode Gowin FPGA products include GW2A (R) series high-performance SRAM devices based on and small capacity nonvolatile device of GW1N (R/S) devices that have built-in Flash. Any configuration data that is stored on the SRAM device is lost after it is powered down; as such, it will need to be reconfigured each time it is powered up.
FPGA has been configured, and the user can use this information to analyze the state of the device accordingly. Please refer to Gowin Programmer guide for the meaning of the status register. Only bitstream data that is without security bit supports validation during SRAM configuration.
5Configuration Mode 5.1Configuration Notes working state. During programming, the B version device works according to the previous configuration. After programming, provide one low pulse for RECONFIG_N to complete the online upgrade. This feature applies to the applications with long online time and irregular upgrades. Pin Multiplexing In different configuration modes, users need to ensure that FPGA works in the selected configuration mode according to the functions of pins.
5Configuration Mode 5.1Configuration Notes Corresponding MODE Value The corresponding relationship between the value of MODE [2:0] and the configuration MODE is shown in Table 5-1. Table 5-1Corresponding MODE Value Configuration GW1N(R/S) GW2A(R) JTAG AUTO BOOT SSPI MSPI GowinCONFIG DUAL 100/110 BOOT SERIAL Note!
5Configuration Mode 5.1Configuration Notes Figure 5-3 Trigger Timing Table 5-2 shows the timing parameters of GW1N(R) series of FPGA products. Table 5-2 Timing Parameters for Cycling Power and RECONFIG_N Trigger Name Description Min. Max. Time from application of V and V to the 50 μs 200 μs...
IEEE1532 standard and the IEEE1149.1 boundary scan standard. The JTAG configuration mode writes bitstream data to the SRAM of Gowin FPGA products. All configuration data is lost after the device is powered down. All Gowin FPGA products support the JTAG configuration mode.
Flash programming. In addition, Gowin FPGA products support JTAG daisy chain operation, which connects the FPGA TDO pin to the next FPGA TDI pin. Gowin programming software will automatically identify the connected FPGA devices and configures in order of the chain. The connection diagram for the daisy chain configuration is shown in Figure 5-5.
5Configuration Mode 5.2JTAG Configuration Figure 5-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode JTAG PORT FPGA FPGA FPGA Note! DONE, RECONFIG_N, and READY can be connected or not according to the actual conditions. JTAG Configuration Timing See Figure5-6 for the JTAG timing. Figure5-6 JTAG Configuration timing See Table 5-5 for the MSPI timing diagram.
RECONFIG_N pins. When the MODE value is adjusted to "000", the FPGA will automatically configure the SRAM to complete AUTO BOOT after the built-in Flash is programmed using Gowin programmer. The instantaneous connection feature with the built-in Flash saves download time and improves productivity.
5Configuration Mode 5.4SSPI 5.4 SSPI In SSPI (Slave SSPI) mode, Gowin FPGA products are configured from an external host via SPI. Pins for the SSPI Mode The SSPI configuration pins are shown in Table 5-6. Table 5-6 SSPI Mode Pins...
FPGA. The MODE value of the Flash programming operation is the same as the MODE value of SSPI; configuration data can be written to SRAM or an external Flash using Gowin programmer. The connection diagram for SSPI interface programming via an external Flash is shown in Figure 5-8.
5Configuration Mode 5.5MSPI See Table 5-7 for the SPPI configuration timing parameters. Table 5-7 SSPI Configuration Timing Parameters Name Description Min. Max. SCLK clock period 15ns sclkp SCLK clock high time 7.5ns sclkh SCLK clock low time 7.5ns sclkl SSPI PORT setup time sspis SSPI PORT hold time sspih...
5Configuration Mode 5.5MSPI Pins for the MSPI Mode The configuration of the MSPI mode is shown in Table 5-8. Table 5-8 Pin Description in JTAG Configuration Mode Pin Name Description Internal RECONFIG_N Low level pulse: Start GowinCONFIG weak pull-up High-level pulse: The device can be programmed and configured;...
5Configuration Mode 5.5MSPI Connection Diagram for the MSPI Configuration Mode The connection diagram for configuring Gowin FPGA products through MSPI is shown in Figure 5-10. Figure 5-10 MSPI Configuration Mode Connection Diagram FPGA SPI Flash FASTRD_N MCLK MCS_N CS_N DOUT Note! The figure above shows the minimum system diagram for the MSPI MODE.
Page 39
ID validation, false CRC check, and false instruction. The user can specify the SPI Flash address of the retry configuration operation, and write it through the Gowin software interface. This feature greatly reduces the risk of configuration failure, and, thereby, ensures higher reliability of the user design.
MSPI support this mode. Refer to the following steps for MULTI BOOT: 1. Open "BItStream" in Gowin YunYuan software. Input the start address for the next BitStream in the text box following "SPI Flash Address", as shown in Figure 5-12;...
ADDR [23:12] can be set. In addition to the introduction of configuring one FPGA via one Flash, Gowin FPGA products support configuring multiple FPGA via one Flash: FPGA devices that are attached directly to the SPI Flash adopts MSPI mode, while the other FPGA devices use the SSPI or SERIAL mode. For the specific operation, see the updated version.
5.5MSPI Before configuring, adjust the MODE value of the FPGA to MSPI and SERIAL or MSPI and SSPI. Gowin FPGA products do not support multi-chip Flash configuration with single FPGA. Figure 5-14 Connection Diagram for Configuring Multi-Chip FPGA via Single...
5.6AUTO BOOT Configuration (supported by GW1N(R/S) 5Configuration Mode only) 5.6 AUTO BOOT Configuration (supported by GW1N(R/S) only) The Dual-Boot mode is a configuration mode supported by the GW1N (R/S) series of nonvolatile FPGA products. In the dual boot mode, FPGA autonomously chooses to read bitstream data from the built-in Flash or external Flash to complete the configuration.
When the MODE value is "110", the devices can start from the external Flash with different addresses. Three attempts are possible. Write the address to bitstream data through Gowin software before starting. If the configuration fails three times, the devices attempt to configure the device from the built-in Flash.
5Configuration Mode 5.7CPU Mode 5.7 CPU Mode In CPU mode, the Host configures Gowin FPGA products through the bus interface with 8-bit data. The pins employed in the CPU mode are shown in Table 5-10. Table 5-10 CPU Mode Pins...
5.8SERIAL RECONFIG_N. 5.8 SERIAL In SERIAL mode, the Host configures Gowin FPGA products via a serial interface. SERIAL is the configuration mode that uses the least number of pins. The SERIAL mode can only write bitstream data to FPGA and cannot readback data from FPGA devices; as such, the SERIAL mode cannot read information on the ID CODE and USER CODE and status register.
Page 47
5Configuration Mode 5.8SERIAL Initiate new program Power-on again or provide one low pulse for programming pin RECONFIG_N. UG290-1.04EUG290-1.04E 40(50)
6Bitstream File Configuration Bitstream File Configuration The features of Gowin FPGA products need to be configured and programmed using Gowin software. The settings mainly include configuration pins multiplexing options and bitstream data configuration options. This chapter describes the bitstream file configuration. For the details about the configuration pins reuse, pelase refer to 4.1.2Pin...
Figure 6-1 Configuration Options Note! Forcibly check the security bit setting after the Gowin software verifies the encryption key setting option. In addition to ensuring the data is secure during the transmission process, using these bitstream settings during configuration also prevents any readback, thereby ensuring maximum protection of user data.
READY and DONE are pulled down. Enter the Encryption KEY Refer to the steps below to write the encryption keys in Gowin software: 1. Open the corresponding project in Gowin software;...
Note! The initial value of the Gowin FPGA keys is 0. If a key value is changed to 1, it cannot be changed back to 0. For example, the key value written during an operation is 00000000-00000000-00000000-00000001, and the last bit of the modified key must be 1.
6.3 Configuration File Size Gowin FPGA product configuration data currently only supports binary format, while the file named as suffix .fs generated by Gowin software is a text format. The user can transform the text file into a binary format via the transformation tool that is available in the programming software: 1.
Gowin programmer can be used to configure GowinFPGA by following the steps outlined below. 1. Connect the device that needs to be configured; 2. Start the Gowin programmer and initiate the scan to identify the connected FPGA device; 3. Select the bitstream and configuration mode to configure the device.
Page 54
Flash according to the user mode selected. (On-chip Flash is supported by GW1N(R) series of FPGA products only.) If the data is loaded to the SRAM, Gowin Yunyuan software will set the security bit automatically in the process of bitstream generation. No user can read SRAMs.
To perform a boundary scan, follow the steps outlined below: 1. Connect the FPGA development board to the PC and power up; 2. Open the Gowin programmer and scan the connected devices; 3. Double-click on the "Operation" field and select "External Flash Mode"...
8Boundary Scan Figure 8-1 Boundary Scan Operation Schematic Diagram The boundary scan operation can only be performed on the external Flash of the FPGA and cannot be used for built-in Flash or SRAM. This operation is irrelevant in the FPGA MODE, but it is slower than external Flash programming during MSPI operation.
Note! The Flash read instructions supported by the Gowin FPGA must have at least one type of 03 or 0B. Use the regular reading command if the clock frequency is no higher than 30 MHz. Use the fast reading instruction if the clock frequency is higher than 30 MHz. Pull down the FASTRD_N pin and ensure the clock frequency is not higher than 80 MHz when reading data quickly .
Need help?
Do you have a question about the GW1N Series and is the answer not in the manual?
Questions and answers