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GOWIN Manuals
Semiconductors
LittleBee Series
Programming and configuration manual
GOWIN LittleBee Series Programming And Configuration Manual
Fpga products
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
List of Figures
About this Guide
Purpose
Related Documents
Terminology and Abbreviations
Table 1-1 Abbreviations and Terminology
Support and Feedback
Glossary
Table 2-1 Glossary
Configuration Modes
Littlebee ® Family of FPGA Products
Arora Family of FPGA Products
Table 3-1 Configuration Modes
Table 3-2 Configuration Modes
Configuration Pin
Configuration Pin List and Reuse Options
Configuration Pin List
Table 4-1 Configuration Pin List
Configuration Pin Multiplexing
Table 4-2 Pin Reuse Options
Configuration Pin Function and Application
Figure 4-1 Configuring Pin Reuse
Table 4-3 Pin Function
Figure 4-2 MCLK Frequency Setting
Configuration Mode Introduction
Configuration Notes
Figure 5-1 Recommended Pin Connection
Figure 5-2 Power Recycle Timing
JTAG Configuration
Figure 5-3 Trigger Timing
Table 5-1 Timing Parameters for Cycling Power and RECONFIG_N Trigger
Table 5-2 Timing Parameters for Power-On Again and RECONFIG_N Triggering (Arora Family)
JTAG Configuration Mode Pins
Table 5-3 Pin Description in JTAG Configuration Mode
Connection Diagram for the JTAG Configuration Mode
Figure 5-4 Connection Diagram for JTAG Configuration Mode
JTAG Configuration Timing
Figure 5-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode
Figure 5-6 JTAG Configuration Timing
Table 5-4 JTAG Configuration Timing Parameters
JTAG Configuration Process
Figure 5-7 TAP State Machine
Figure 5-8 Instruction Register Access Timing
Figure 5-9 Data Register Access Timing
Table 5-5 Gowin FPGA IDCODE
Table 5-6 Change of TDI and TMS Value in the Process of Sending Instructions
Figure 5-10 Read Machine Flow Chart in ID Code State
Figure 5-11 the Access Timing of Read ID Code Instruction- 0X11
Figure 5-12 Read ID Code Data Register Access Timing
Figure 5-13 SRAM Configuration Flow
Table 5-7 Count of Address and Length of One Address
Figure 5-14 Process of Reading SRAM
Table 5-8 TCK Frequency Requirements for JTAG
Figure 5-15 the Embedded Flash Erasing Process of T Technology
Figure 5-16 the Embedded Flash Erasing Process of S Technology
Table 5-9 Readback-Pattern / Autoboot-Pattern
Figure 5-17 Process of Programming Internal Flash View
Figure 5-18 X-Page Programming
Figure 5-19 Y-Page Programming
Figure 5-20 Process of Reading Internal Flash
Figure 5-21 Process of Reading a Y-Page
Figure 5-22 GW1N-4 Background Programming Flow
Figure 5-23 Transfer JTAG Instruction Sample & Extest Flow Chart
Figure 5-24 Connection Diagram of JTAG Programming External Flash
Figure 5-25 Process View of Programming SPI Flash SPI
Figure 5-26 Timing Diagram of Sending 0X06 Via GW2A Series JTAG Simulating SPI
Figure 5-27 Timing Diagram of Sending 0X06 Via GW1N Series JTAG Simulating SPI
Table 5-10 Pin State
Figure 5-28 Process of Use Boundary Scan Mode to Program SPI Flash
Table 5-11 Status Register Definition
AUTO BOOT Configuration (Supported by Littlebee Family Only)
Figure 5-29 Connection Diagram of Daisy-Chain
Sspi
SSPI Mode Pins
Table 5-12 SSPI Mode Pins
SSPI Configuration Timing
Configuration Instruction
Figure 5-30 SSPI Configuration Timing
Table 5-13 SSPI Configuration Timing Parameters
Figure 5-31 Read ID Code Timing
Table 5-14 Configuration Instruction
Figure 5-32 Write Enable (0X15) Timing
Figure 5-33 Write Disable(0X3A00) Timing
Figure 5-34 Write Data (0X3B) Timing
Connection Diagram for SSPI Configuration Mode
Figure 5-35 SSPI Configuration Mode Connection Diagram
Figure 5-36 Connection Diagram of Programming External Flash Via SSPI
Figure 5-37 the Flow of Programming External Flash Via SSPI
Multiple FPGA Connection View in SSPI Mode
Mspi
Figure 5-38 Multiple FPGA Connection Diagram 1
Figure 5-39 Multiple FPGA Connection Diagram 2
Table 5-15 Pin Description in JTAG Configuration Mode
Figure 5-40 Connection Diagram for MSPI Configuration Mode
Figure 5-41 Connection Diagram of JTAG Programming External Flash
Figure 5-42 Input the Start Address for the Next Bitstream
Figure 5-43 Set the Programming Address for the External Flash
Figure 5-44 Connection Diagram for Configuring Multiple Fpgas Via Single Flash
Figure 5-45 MSPI Download Timing
DUAL BOOT Configuration (Supported by Littlebee Family Only)
Figure 5-46 Multiple FPGA Connection Diagram in MSPI Configuration Mode
Table 5-16 MSPI Configuration Timing Parameters
Figure 5-47 Dual Boot Flow Chart
CPU Mode
Table 5-17 CPU Mode Pins
Configuration Timing
SERIAL Mode
Figure 5-48 Connection Diagram for CPU Mode
Figure5-49 CPU Mode Configuration Timing
Figure 5-50 Connection Diagram for SERIAL Mode
Figure 5-51 SERIAL Configuration Timing
Table 5-18 Pin Definition in SERIAL Configuration Mode
I 2 C Mode
Table 5-19 SERIAL Configuration Timing Parameters
Table 5-20 Pin Definition in SERIAL Configuration Mode
Figure 5-52 Connection Diagram for I 2 C Mode
Figure 5-53 I 2 C Mode Timing
Table 5-21 I 2 C Configuration Timing Parameters
Bitstream File Configuration
Configuration Options
Configuration Data Encryption (Supported by Arora Family Only)
Definition
Figure 6-1 Configuration Options
Enter Encryption KEY
Enter the Decrypt Key
Figure 6-2 Encryption Key Setting Method
Programming Operation
Figure 6-3 Setting the Decryption Key
Figure 6-4 AES Security Configure
Programming Flow
Figure 6-5 Prepare
Figure6-6 Read AES Key Flow
Figure 6-7 Program AES Key Flow
Configuration File Size
Figure 6-8 Lock AES Key Flow
Configuration File Loading Time
Figure 6-9 Bitstream Format Generation
Table 6-1 Gowin FPGA Products Configuration File Size (Max.)
Table 6-2 Loading Frequency of Config File
Table 6-3 Loading Time in MSPI Mode
Table 6-4 Loading Time in Autoboot Mode
Safety Precautions
Boundary Scan
Figure 8-1 Boundary Scan Operation Schematic Diagram
SPI Flash Selection
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Gowin FPGA Products
Programming and Configuration Guide
UG290-2.3E, 02/07/2021
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This manual is also suitable for:
Arora series
Gw2a-55
Gw2a-55c
Gw2a-18
Gw2a-18c
Gw2ar-18
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Gw2ar-18c
Gw2anr-18c
Gw1n-1
Gw1n-1s
Gw1ns-2
Gw1nsr-2
Gw1ns-2c
Gw1nsr-2c
Gw1nse-2c
Gw1nz-1
Gw1n-2
Gw1n-2b
Gw1nser-4c
Gw1ns-4
Gw1nsr-4
Gw1ns-4c
Gw1nsr-4c
Gw1n-4b
Gw1nr-4b
Gw1nrf-4b
Gw1n-4
Gw1nr-4
Gw1n-6
Gw1n-9
Gw1n-9c
Gw1nr-9
Gw1nr-9c
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