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Revision History Date Version Description 09/10/2018 1.0E Initial version published (Preliminary). 11/22/2018 1.1E Pins distribution view for different packages added. Quantity of GW1NS-2/GW1NS-2C Pins updated; 01/10/2019 1.2E Introduction to the I/O BANK updated. 04/03/2019 1.3E CS36 package outline updated. 10/12/2019 1.4E GW1NS-4 / GW1NS-4C added.
Contents Contents Contents ....................... i List of Figures ..................... ii List of Tables ...................... iii 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Abbreviations and Terminology ................... 1 1.4 Support and Feedback ....................... 1 2 Overview ......................
List of Figures List of Figures Figure 2-1 GW1NS I/O Bank Distribution ..................6 Figure 3-1 View of GW1NS-4/GW1NS-4C CS49 Pins Distribution (Top View) ......... 8 Figure 3-2 View of GW1NS-4/GW1NS-4C QN48 Pins Distribution (Top View) ......... 9 Figure 3-3 View of GW1NS-4/GW1NS-4C MG64 Pins Distribution (Top View) ........ 10 Figure 4-1 Package Outline CS49 .....................
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Table 2-2 GW1NS Power Pins ......................3 Table 2-3 Quantity of GW1NS-4/GW1NS-4C Pins ................3 Table 2-4 Definition of the Pins in the GW1NS series of FPGA Products ......... 4 Table 3-1 Other pins in GW1NS-4/GW1NS-4C CS49 ............... 8 Table 3-2 Other pins in GW1NS-4/GW1NS-4C QN48 ............... 9 Table 3-3 Other pins in GW1NS-4/GW1NS-4C MG64 ..............
1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose This manual contains an introduction to the GW1NS series of FPGA products together with a definition of the pins, list of pin numbers, distribution of pins, and package diagrams. 1.2 Related Documents The latest user guides are available on GOWINSEMI Website.
Things, servo drive, consumption fields, etc. 2.1 PB-Free Package The GW1NS series of FPGA products are PB free in line with the EU ROHS environmental directives. The substances used in the GW1NS series of FPGA products are in full compliance with the IPC-1752 standards.
2 Overview 2.3 Power Pins this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O plus one. 2.3 Power Pins Table 2-2 GW1NS Power Pins VCCO0...
2 Overview 2.5 Pin Definitions 2.5 Pin Definitions The location of the pins in the GW1NS series of FPGA products varies according to the different packages. Table 2-4 provides a detailed overview of user I/O, multi-function pins, dedicated pins, and other pins.
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2 Overview 2.5 Pin Definitions Pin Name Description pull-up Access SPI FLASH to select signal. Low, Fast Read FASTRD_N mode; High, Read mode. High, the device can be programmed and configured currently; READY Low, the device cannot be programmed and configured currently.
[2] When the input is single-ended, the GLKC_[x] pin is not a global clock pin. 2.6 Introduction to the I/O BANK There are four I/O Banks in the GW1NS series of FPGA products, as shown in Figure 2-1. Figure 2-1 GW1NS I/O Bank Distribution This manual provides an overview of the distribution view of the pins in the GW1NS series of FPGA products.
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2 Overview 2.6 Introduction to the I/O BANK " " denotes VCC. The filling color does not change. " " denotes VSS. The filling color does not change. " " denotes NC. UG823-1.8E 7(13)
3 View of Pin Distribution 3.1 View of GW1NS-4/GW1NS-4C Pins Distribution View of Pin Distribution 3.1 View of GW1NS-4/GW1NS-4C Pins Distribution 3.1.1 View of CS49 Pins Distribution Figure 3-1 View of GW1NS-4/GW1NS-4C CS49 Pins Distribution (Top View) Table 3-1 Other pins in GW1NS-4/GW1NS-4C CS49 VCCO1 VCCO2 VCCX...
3 View of Pin Distribution 3.1 View of GW1NS-4/GW1NS-4C Pins Distribution 3.1.2 View of QN48 Pins Distribution Figure 3-2 View of GW1NS-4/GW1NS-4C QN48 Pins Distribution (Top View) Table 3-2 Other pins in GW1NS-4/GW1NS-4C QN48 11,37 VCCO0 VCCO1 VCCO2 VCCO3 12,24 VCCX UG823-1.8E 9(13)
3 View of Pin Distribution 3.1 View of GW1NS-4/GW1NS-4C Pins Distribution 3.1.3 View of MG64 Pins Distribution Figure 3-3 View of GW1NS-4/GW1NS-4C MG64 Pins Distribution (Top View) Table 3-3 Other pins in GW1NS-4/GW1NS-4C MG64 VCCO0 VCCO1 VCCO2 VCCO3 VCCX D4,E5 UG823-1.8E 10(13)
4 Package Diagrams 4.1 CS49 Package Outline (2.9mm x 2.9mm) Package Diagrams 4.1 CS49 Package Outline (2.9mm x 2.9mm) Figure 4-1 Package Outline CS49 PIN 1(A1 ) 0.33099925 G W 1 N S - L V 4 C S 4 9 C 6 Y W W X X X X X X X X 0.23082475...
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