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GOWIN LittleBee GW1N Series Programming And Configuration Manual

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Gowin FPGA Products
Programming and Configuration Guide
UG290-2.5.2E, 07/14/2022

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  • Page 1 Gowin FPGA Products Programming and Configuration Guide UG290-2.5.2E, 07/14/2022...
  • Page 2 Copyright © 2022 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , Gowin, LittleBee, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Revision History Date Version Description 4/17/2017 1.00E Initial version published.  Configuration mode and value of different supported device updated; 5/31/2017 1.01E  RECONFIG N notes during programming built-in Flash updated. 10/13/2017 1.02E Description of reusing pins updated. 3/16/2018 1.03E GW1NS programming and configuration description added.

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ....................... v 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ..................1 1.4 Support and Feedback ....................... 2 2 Glossary ......................
  • Page 5 Contents 6.3 AUTO BOOT Configuration (Supported by LittleBee ® Family Only) ........ 55 6.4 SSPI ..........................57 6.4.1 SSPI Mode Pins ......................57 6.4.2 SSPI Configuration Timing .................... 58 6.4.3 Configuration Instruction ....................58 6.4.4 Connection Diagram for SSPI Configuration Mode ............62 6.4.5 Multiple FPGA Connection View in SSPI Mode ............

  • Page 6: List Of Figures

    List of Figures List of Figures Figure 4-1 POR Power-up Timing ...................... 10 Figure 5-1 Configuring Pin Reuse ..................... 16 Figure 5-2 MCLK Frequency Setting ....................19 Figure 6-1 Recommended Pin Connection ..................23 Figure 6-2 Power Recycle Timing ...................... 24 Figure 6-3 Trigger Timing ........................
  • Page 7 List of Figures Figure 6-29 Timing Diagram of Sending 0x06 via GW1N series JTAG Simulating SPI ....52 Figure 6-30 Process of Use Boundary Scan Mode To Program SPI Flash ........53 Figure 6-31 Connection Diagram of Daisy-Chain ................55 Figure 6-32 SSPI Configuration Timing .....................
  • Page 8 Table 6-20 Pin Definition in SERIAL Configuration Mode ..............77 Table 6-21 I C Configuration Timing Parameters ................78 Table 7-1 Gowin FPGA Products Configuration File Size (Max.) ............90 Table 7-2 Loading Frequency of Config File ..................92 Table 7-3 Loading Time in MSPI Mode ....................93...
  • Page 9 List of Tables Table 7-4 Loading Time in Autoboot Mode ..................93 Table 10-1 SPI Flash Operation Instruction ..................98 UG290-2.5.2E...

  • Page 10: About This Guide

    This guide mainly introduces general features and functions on programming and configuration of LittleBee ® family devices and Arora family devices. It helps users to use Gowin FPGA products to their full potential. 1.2 Related Documents The latest user guides are available on the GOWINSEMI Website. You can find the related documents at www.gowinsemi.com:...

  • Page 11: Support And Feedback

    I2C (I C、IIC) Serial Clock Serial Data 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com E-mail:support@gowinsemi.com UG290-2.5.2E...

  • Page 12: Glossary

    2 Glossary Glossary This chapter presents an overview of the terms that are commonly used in the process of programming and configuring of Gowin FPGA products to help users get familiar with the related concepts. Table 2-1 Glossary Glossary Meaning...
  • Page 13 Security Bit the device SRAM, no one will be able to read back the data. Gowin software sets a security bit for the bitstream data of all FPGA products by default. The Arora family of FPGA products supports this feature. After...

  • Page 14: Configuration Modes

    3 Configuration Modes 3.1 LittleBee® Family of FPGA Products Configuration Modes 3.1 LittleBee Family of FPGA Products ® Besides the JTAG configuration mode that is commonly used in the ® industry, the LittleBee Family of FPGA products also support GOWINSEMI's own configuration mode: GowinCONFIG. GowinCONFIG configuration modes that are available and supported for each device depend on the device model and package.

  • Page 15: Table 3-1 Configuration Modes

    3 Configuration Modes 3.1 LittleBee® Family of FPGA Products Table 3-1 Configuration Modes Configuration Modes MODE[2:0] Description ® The LittleBee Family of FPGA products JTAG are configured via JTAG interface by external Host. AUTO FPGA reads data from embedded Flash BOOT for configuration FPGA products are configured via I...

  • Page 16: Arora Family Of Fpga Products

    3 Configuration Modes 3.2 Arora Family of FPGA Products 3.2 Arora Family of FPGA Products Besides the JTAG configuration mode that is commonly used in the industry, the Arora Family of FPGA products also support GOWINSEMI's own configuration mode: GowinCONFIG. The GowinCONFIG configuration modes that are available and supported for each device depend on the device model and package.

  • Page 17: Configuration Process

    4 Configuration Process Configuration Process After power on, the FPGA goes through a sequence of states including initialization, SRAM configuration, and wake-up. The configuration flow is as shown in below. UG290-2.5.2E 8(98)
  • Page 18 4 Configuration Process Figure 4-1 Configuration Flow Power Up (VCC/VCCO/VCCX meets power requirements) READY and DONE Internal Driven Low RECONFIG_N or READY = Low Initialization RECONFIG_N = High READY Driven High and MODE Value Sampled RECONFIG_N Driven Write SRAM ERROR Low or Device Refresh Memory and READY = Low...

  • Page 19: Power-Up Sequence

    4 Configuration Process 4.1 Power-up Sequence 4.1 Power-up Sequence During the power-on process, the power-on reset (POR) circuit inside the FPGA becomes active. The actie POR circuit makes sure the external I/O pins are in a high-impedance state and monitors the VCC/VCCX/VCCOn input rails.

  • Page 20: Initialization

    4 Configuration Process 4.2 Initialization Power Rails Series Device GW2AN-18X GW2AN-55 VCC/VCCX/VCCO3 GW2ANR GW2ANR-18 VCC/VCCX/VCCO3 4.2 Initialization After the power on reset circuit drives the READY and DONE status pins low, the FPGAs enter the memory initialization immediately. The purpose of the initialization is to clear all the SRAM memory inside the FPGA.

  • Page 21: User Mode

    4 Configuration Process 4.5 User Mode 4.5 User Mode After entering user mode, the FPGA will perform the logic operations you designed immediately. The FPGA will remains in this state until one of the following three events occurs: The RECONFIG_N pin is externally driven low. ...

  • Page 22: Configuration Pin

    5.1 Configuration Pin List and Reuse Options 5.1.1 Configuration Pin List Table 5-1 contains a list of all the configuration pins of Gowin FPGA products together with the details of the pins used in each configuration mode and the shared pins in chip packages.

  • Page 23: Configuration Pin Reuse

    To maximize the utilization of I/O, Gowin FPGA products support setting the configuration pins as GPIO pins. Before any configuration operation is performed on all series of Gowin FPGA products after power up, all related configuration pins are used as configuration pins by default.

  • Page 24: Table 5-2 Pin Reuse Options

    GPIOs separately. However, the pins can be set as GPIOs in non-shared configuration modes. Configure Dual-purpose Pin The steps are as follows: 1. Open the project in Gowin software; 2. Select “Project > Configuration > Dual Purpose Pin” from the menu options, as shown in ; UG290-2.5.2E...

  • Page 25: Configuration Pin Function And Application

    5.2 Configuration Pin Function and Application The RECONFIG_N, READY, and DONE pins are used in all configuration modes. Other pins can be set as dedicated pins or GPIO (Gowin Programmable IO) according to their specific application. Table 5-3 Pin Function Pin Name...
  • Page 26 As a configuration pin, it is an input pin with internal weak pull-up. If JTAG pins are set as a GPIO in the Gowin software, the JTAG pins can become GPIOs after the device being powered up and successfully configured.
  • Page 27 5 Configuration Pin 5.2 Configuration Pin Function and Application Pin Name Functional Description ® For the LittleBee Family of FPGA products, when MODE[2: 0]=001, the JTAGSEL_N pin and the four JTAG pins (TCK, TMS, TDI, TDO) can be set as GPIOs simultaneously, but the JTAG pin cannot be recovered as a configuration pin by JTAGSEL_N.

  • Page 28: Figure 5-2 Mclk Frequency Setting

    125 MHz clock. Please refer to the corresponding device datasheet for further detailed data on the on-chip crystal oscillator. The MCLK frequency values can be modified through the Gowin software interface, as shown in Figure 5-2. Open Gowin software, select "Project >...
  • Page 29 5 Configuration Pin 5.2 Configuration Pin Function and Application Pin Name Functional Description Data input/output pins in CPU configuration mode, 8-bit width. Determine the input/output of D0 ~ D7 according to WE_N. As a GPIO, it can be used as an input or output type. As a configuration pin, it is an input pin with internal weak pull-up.

  • Page 30: Configuration Mode Introduction

    AUTOBOOT or DUALBOOT configuration options. Gowin FPGA products have abundant packages. The configuration modes supported by each device are related to the number of configuration pins bonded out: All devices support JTAG configuration, but only non-volatile devices support AUTO BOOT or DUAL BOOT configuration.
  • Page 31 6 Configuration Mode Introduction 6.1 Configuration Notes RECONFIG_N can be left floating or externally pulled up. All GPIOs output high impedance state before FPGA is waken up. GOWINSEMI FPGA products write bitstream data to SRAM, on-chip Flash, or off-chip Flash according to the data storage and the instructions. Only the LittleBee ®...

  • Page 32: Figure 6-1 Recommended Pin Connection

    6 Configuration Mode Introduction 6.1 Configuration Notes Note! The RECONFIG_N, READY, and DONE pins are associated with each configuration mode. Whether they are set as GPIO or not, users should ensure that their initial value or pin connection state meets programming and configuration conditions before completing the configuration process.

  • Page 33: Figure 6-2 Power Recycle Timing

    6 Configuration Mode Introduction 6.1 Configuration Notes Figure 6-2 Power Recycle Timing Figure 6-3 Trigger Timing ® Timing parameters of the LittleBee Family of FPGA Products is as shown in Table 6-1 . Table 6-1 Timing Parameters for Cycling Power and RECONFIG_N Trigger Name Description Min.

  • Page 34: Jtag Configuration

    IEEE1532 standard and the IEEE1149.1 boundary scan standard. The JTAG configuration mode writes bitstream data to the SRAM of Gowin FPGA products. All configuration data is lost after the device is powered down. All Gowin FPGA products support the JTAG configuration mode.

  • Page 35: Connection Diagram For The Jtag Configuration Mode

    Figure In addition, Gowin FPGA products support JTAG daisy chain operation, which connects the FPGA TDO pin to the next FPGA TDI pin. Gowin programming software will identify the connected FPGA devices automatically and configure them in turn. The connection diagram for the daisy chain configuration is shown in Figure 6-5.

  • Page 36: Jtag Configuration Timing

    6 Configuration Mode Introduction 6.2 JTAG Configuration Figure 6-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode JTAG PORT FPGA FPGA FPGA Note! DONE, RECONFIG_N, and READY can be connected or not as appropriate. 6.2.3 JTAG Configuration Timing See Figure 6-6 for the timing of JTAG mode. Figure 6-6 JTAG Configuration timing See Table 6-4 for the description of timing parameters.

  • Page 37: Jtag Configuration Process

    6 Configuration Mode Introduction 6.2 JTAG Configuration 6.2.4 JTAG Configuration Process TAP State Machine The state machine for the test access port is designed to select an instruction register or a data register to connect it between TDI and TDO. In general, the instruction register is used to select the data register to be scanned.

  • Page 38: Figure 6-8 Instruction Register Access Timing

    ID Code, i.e. JEDEC ID Code, is a basic identification of FPGA products. The length of the Gowin FPGA ID Code is 32 bits. The ID Codes of the FPGA are listed in the following table. Table 6-5 Gowin FPGA IDCODE Gowin FPGA Device Family IDCODE UG290-2.5.2E...

  • Page 39: Table 6-6 Change Of Tdi And Tms Value In The Process Of Sending Instructions

    6 Configuration Mode Introduction 6.2 JTAG Configuration Device Part Manufacturer ID Device Family Bits 11-0 IDCODE Bits 31-12 h81B GW1N-1 h09002 h0900281B GW1N-1S h09003 h0900381B GW1NZ-1 h01006 h0100681B GW1NS-2 h03000 h0300081B GW1NS(R)-2C h03001 h0300181B GW1NSE-2C h03001 h0300181B GW1N-2/2B h01206 h0120681B GW1N-1P5/1P5B h01206 h0120681B...

  • Page 40: Figure 6-10 Read Machine Flow Chart In Id Code State

    6 Configuration Mode Introduction 6.2 JTAG Configuration period, sending 32 clocks can read 32 bits data, that is, 0x0100381B, as shown in Figure 6-12; 6. Move the state machine back to Run-Test-Idle; Figure 6-10 Read Machine Flow Chart in ID Code State Start Move TAP to Shift-DR Move TAP to Shift-IR...
  • Page 41 FPGA functions. SRAM is configured via JTAG to avoid the influence of Configuration Mode Pins. Generate the FS file using Gowin software. Configure SRAM via JTAG. The process of SRAM configuration using the external Host is as follows, as shown in Figure 6-13.

  • Page 42: Figure 6-13 Sram Configuration Flow

    6 Configuration Mode Introduction 6.2 JTAG Configuration Figure 6-13 SRAM Configuration Flow Check See Read Flow ID Code SRAM Erase (Option) Transfer Config Enable Instruction (0x15) Transfer Address Init Instruction (0x12) Transfer Write Instruction (0x17) Transfer Bitstream(MSB) Transfer Config Disable Instruction (0x3A) Transfer NOOP Instruction...

  • Page 43: Table 6-7 Count Of Address And Length Of One Address

    6 Configuration Mode Introduction 6.2 JTAG Configuration (high level). During loading, FPGA performs CRC check on the written data to ensure that the data is written correctly, and whether CRC reports an error can be used as a check mechanism to configure SRAM. Table 6-7 Count of Address and Length of One Address Device Length of One Address (bits/address)

  • Page 44: Figure 6-14 Process Of Reading Sram

    6 Configuration Mode Introduction 6.2 JTAG Configuration Figure 6-14 Process of reading SRAM Start Transfer Config Enable Instruction (0x15) Transfer Initialize Address Instruction (0x12) Transfer Read Instruction (0x03) Next address is valid Read data of one address Compute the checksum(16bit) Transfer Config Disable Instruction (0x3A)
  • Page 45 6 Configuration Mode Introduction 6.2 JTAG Configuration 7. Send the "0x02” instruction of Noop to end the Erasure process. Note! You need to wait enough time for the device to finish erasing after the instructions of EraseSram(0x05) and Noop(0x02) are sent. The reference time for GW1N(*)-1 is 1ms;...

  • Page 46: Figure 6-15 Process Of Normal Programming

    6 Configuration Mode Introduction 6.2 JTAG Configuration Figure 6-15 Process of Normal Programming Start Verify ID Code Read Status DoneFinal=1 Erase SRAM DoneFinal=0 Erase Flash Send Reconfig Instruction(0x3C) DoneFinal=1 Sleep 10ms Read Status DoneFinal=0 If need to read back to verify data, Please use Readable-pattern at the 1 Y-page of the 1 X-page.

  • Page 47: Figure 6-16 Process Of Background Programming

    6 Configuration Mode Introduction 6.2 JTAG Configuration Figure 6-16 Process of Background Programming Start Verify ID Code Erase Flash If need to read back to verify data, Please use Readable-pattern at the 1 Y-page of the 1 X-page. Program Flash Stop Erase Internal Flash For the embedded Flash memory of GW1N series, the embedded...
  • Page 48 6 Configuration Mode Introduction 6.2 JTAG Configuration 5. Send the "0x75" instruction of EFlash Erase; 6. The clock（Run-Test） is continuously generated in Run-Test-Idle for 500μs; 7. Move the state machine in turn: Run-Test-ldle -> Select-DR-Scan-> Capture-DR -> Shift-DR -> Transfer 32 bits-> Exit1-DR -> Update-DR -> Run-Test-ldle (This step only applied to GW1N-4.Skip this step for other devices);...

  • Page 49: Figure 6-17 The Embedded Flash Erasing Process Of T Technology

    6 Configuration Mode Introduction 6.2 JTAG Configuration Figure 6-17 The Embedded Flash Erasing process of T Technology Start SRAM Erase Run-Test 500 us Transfer Config Enable Instruction (0x15) Transfer EFlash Erase Instruction (0x75) Move TAP through Run-Test-Idle -> Select-DR-Scan -> Capture-DR -> Shift-DR ->...
  • Page 50 6 Configuration Mode Introduction 6.2 JTAG Configuration Update-DR; 4. Repeat the steps above, 65 times in all; 5. The clock（Run-Test）is continuously generated in Run-Test-Idle for 120ms. Please refer to Table 6-8 for the frequency requirements; 6. Send the "0x3A" instruction of Config Disable; 7.

  • Page 51: Figure 6-18 The Embedded Flash Erasing Process Of H Technology

    6 Configuration Mode Introduction 6.2 JTAG Configuration Figure 6-18 The Embedded Flash Erasing process of H Technology Start Transfer Config Enable Instruction (0x15) Transfer SRAM Erase Instruction (0x05) Run-Test 1ms Transfer SRAM Erase Done Instruction (0x09) Run-Test 500 us Transfer EFlash Erase Instruction (0x75) Repeat 65 times:...

  • Page 52: Table 6-9 Readback-Pattern / Autoboot-Pattern

    6 Configuration Mode Introduction 6.2 JTAG Configuration Note! The condition to erase the second Flash is that FPGA should be in the Wakeup state. (Done Final of Status Code should be 1.) 4. Send the "0x75" instruction of EFlash Erase; 5.

  • Page 53: Figure 6-19 Process Of Programming Internal Flash View

    6 Configuration Mode Introduction 6.2 JTAG Configuration 8. Read Status Code/User Code to check if the loading is successful. Figure 6-19 Process of Programming Internal Flash View Start Check See ReadIDCode ID Code Erase Flash Program the first X-page Verify with readable-pattem Transfer Config Enable Instruction...

  • Page 54: Figure 6-20 X-Page Programming

    6 Configuration Mode Introduction 6.2 JTAG Configuration One X-page has 256 bytes in all. Program 4 Bytes and program 64 times for one Y-page. The Y-page data is written in LSB way. Refer to Figure 6-20. 5. After one X-page is written in, GW1N-1(S) needs to perform Run-Test for 2400μs;...

  • Page 55: Figure 6-21 Y-Page Programming

    6 Configuration Mode Introduction 6.2 JTAG Configuration After one Y-page is written in each time, GW1N(Z)-2/4/6/9 needs to perform Run-Test for 13-15 μs; GW1N(S)-2(C) needs to perform Run-Test for 30-35 μs. No extra clock is required for the other series of devices. Note! If you want to read data from Configuration Data, high 4 Bytes will be taken.

  • Page 56: Figure 6-22 Process Of Reading Internal Flash

    6 Configuration Mode Introduction 6.2 JTAG Configuration X-address in 0; 5. 64 Y-page is an X-page; 6. After reading one X-page, need not to send address again. The address will recurse automatically; 7. After reading, send the "0x3A" instruction of ConfigEnabled to end the process.

  • Page 57: Figure 6-23 Process Of Reading A Y-Page

    6 Configuration Mode Introduction 6.2 JTAG Configuration Figure 6-23 Process of Reading a Y-page Start Move TAP to SHIFT-DR Transfer 4 Bytes(all 0x0), and get Y-page data from TDO, data is LSB. Move TAP to Exit1-DR， Update-DR & Run-Test-Idle Background Programming The device sometimes needs to upgrade the data file and program the Flash without affecting current functions.

  • Page 58: Figure 6-24 Gw1N-4 Background Programming Flow

    6 Configuration Mode Introduction 6.2 JTAG Configuration Figure 6-24 GW1N-4 Background Programming Flow Start Flash Erase Flash Program Verify Flash Readback Transfer JTAG Instructions Sample(0x01) & Extest(0x04) Toggle reconfig_N pin Transfer JTAG Instructions NOOP (0xFF) UG290-2.5.2E 49(98)

  • Page 59: Figure 6-25 Transfer Jtag Instruction Sample & Extest Flow Chart

    Select-DR-Scan Capture-DR Exit1-DR Update-DR Select-DR-Scan Shift-IR (Transfer Extest Instruction 0x04) Update-IR Run-TEST/IDLE Note! Jump directly from Update-IR to Select-DR-Scan. ○ ExFlash Programming Gowin FPGA can load bitstream files from external Flash and program external Flash through JTAG directly. UG290-2.5.2E 50(98)

  • Page 60: Figure 6-26 Connection Diagram Of Jtag Programming External Flash

    6 Configuration Mode Introduction 6.2 JTAG Configuration Figure 6-26 Connection Diagram of JTAG Programming External Flash FPGA Flash MCLK MCS_N CS_N JTAG PORT DOUT Note! The figure above shows the minimum system diagram of programming external Flash via JTAG. Program External Flash via JTAG-SPI In this mode, the external Flash can be programed via JTAG.

  • Page 61: Figure 6-28 Timing Diagram Of Sending 0X06 Via Gw2A Series Jtag Simulating Spi

    6 Configuration Mode Introduction 6.2 JTAG Configuration Figure 6-28 Timing Diagram of Sending 0x06 via GW2A series JTAG Simulating Figure 6-29 Timing Diagram of Sending 0x06 via GW1N series JTAG Simulating Program SPI Flash in JTAG Boundary Scan Mode The principle of this mode is changing the state of the pins connected to SPI by using Boundary Scan method to implement SSPI timing, and then to program the internal Flash.

  • Page 62: Figure 6-30 Process Of Use Boundary Scan Mode To Program Spi Flash

    6 Configuration Mode Introduction 6.2 JTAG Configuration Note! ctrl:0 means output, 1 means input;  data:0 means low, 1 means high.  Figure 6-30 Process of Use Boundary Scan Mode To Program SPI Flash Start Check See RaadIDCode ID Code Transfer Config Enable Instruction (0x15)

  • Page 63: Table 6-11 Status Register Definition

    CRC Error Bad Command Error ID Verify Failed Error Timeout Error Gowin VLD(1) Done Final Security Final Encrypted Ready(1) Ready(0) Ready(1) format POR(1) Encrypted key is right 19-31 Note! * Gowin VLD is associated with the embedded Flash. UG290-2.5.2E 54(98)

  • Page 64: Auto Boot Configuration (Supported By Littlebee Family Only)

    Read ID Code. The user code adopts the checksum value in the FS file by default. It can be redefined using Gowin Designer. Reload 0x3C This instruction is used to read the bitstream files from Flash and write to SRAM.
  • Page 65 When the MODE value is set to "000", the FPGA will automatically configure the SRAM to complete AUTO BOOT after the built-in Flash is programmed using Gowin programmer. The momentary connection feature of the built-in Flash saves download time and improves productivity.

  • Page 66: Sspi

    6 Configuration Mode Introduction 6.4 SSPI 6.4 SSPI In SSPI (Slave SPI) mode, FPGA is as a slave device and is configured via SPI by an external Host. 6.4.1 SSPI Mode Pins The SSPI configuration pins are shown in Table 6-12. Table 6-12 SSPI Mode Pins Pin Name Description...

  • Page 67: Sspi Configuration Timing

    6 Configuration Mode Introduction 6.4 SSPI 6.4.2 SSPI Configuration Timing See Figure 6-32 for the SSPI timing. Figure 6-32 SSPI Configuration Timing See Table 6-13 for the SSPI configuration timing parameters. Table 6-13 SSPI Configuration Timing Parameters Name Description Min. Max.

  • Page 68: Figure 6-33 Read Id Code Timing

    6 Configuration Mode Introduction 6.4 SSPI including at least 1 instruction class byte and multiple redundant information bytes. If there is no specified information byte, the redundant information byte can be any number (0x00 is used in the following table). Table 6-14 Configuration Instruction Name Complete Instruction (Instruction Byte +...

  • Page 69: Figure 6-34 Write Enable (0X15) Timing

    6 Configuration Mode Introduction 6.4 SSPI instructions. Figure 6-34 Write Enable (0x15) Timing Note! At CS high level, more than two clocks should be given to SCLK to drive FPGA to identify CS signal. This rule also applies to other instructions. Write Disable (0x3A00) After finishing sending data, exit programming mode using Write Disable.

  • Page 70: Figure 6-36 Write Data (0X3B) Timing

    6 Configuration Mode Introduction 6.4 SSPI The timing of 0x1500 and 0x3A is basically the same. Instructions start at CS low level and the CS is pulled up after the instruction transmission is completed. Instructions following this timing are as follows: 0x3C00 (Reconfig / Reprogram), 0x1500(Write Enable), 0x3A000 (Write Disable), 0x1600(Program SPI Flash), 0x1200(Init Address), 0x0500(Erase SRAM).

  • Page 71: Connection Diagram For Sspi Configuration Mode

    The MODE value of the Flash programming is the same as the MODE value of SSPI configuration mode. Configuration data can be written to SRAM or an external Flash using Gowin programmer. The connection diagram for programming an external Flash via SSPI is shown in Figure 6-38.

  • Page 72: Multiple Fpga Connection View In Sspi Mode

    6 Configuration Mode Introduction 6.4 SSPI Figure 6-39 The Flow of Programming External Flash via SSPI Start Transfer Program SPI Flash Instruction (0x1600) Program Flash following SPI timing 6.4.5 Multiple FPGA Connection View in SSPI Mode Figure 6-40 Multiple FPGA Connection Diagram 1 Figure 6-41 Multiple FPGA Connection Diagram 2 UG290-2.5.2E 63(98)

  • Page 73: Mspi

    6 Configuration Mode Introduction 6.5 MSPI 6.5 MSPI In MSPI (Master SPI) mode, the FPGA as the Master reads bitstream data from external Flash memory via its SPI port to configure the FPGA’s internal SRAM. MSPI Mode FPGA Configuration: 1. Set the MODE pin configuration values to be MSPI mode. 2.

  • Page 74: Mspi Mode Pins

    The configuration of the MSPI mode is shown in Table 6-15. Table 6-15 Pin Description in MSPI Configuration Mode Pin Name Description RECONFIG_N Low level pulse: Start Gowin CONFIG Internal weak pull-up In non-JTAG configuration mode, READY 1’b1: The device can be programmed and configured.

  • Page 75: Connection Diagram For Mspi Configuration Mode

    6 Configuration Mode Introduction 6.5 MSPI 6.5.2 Connection Diagram for MSPI Configuration Mode The MSPI external Flash interface is shown in Figure 6-42. Figure 6-42 Connection Diagram for MSPI Configuration Mode Note! The figure above shows the minimum system diagram for the MSPI MODE. The value of the MSPI MODE is "010"...

  • Page 76: Mspi Mode Configuration Attempts

    If there is an ID Code error or a bitstream header instruction error, it will not boot from  the specified SPI Flash address. The alternative SPI Flash start address is specified using the GOWIN EDA tool Bitstream option when running Design Place & Route (see Multiboot for more details).

  • Page 77: Figure 6-44 Example Of Bitstream Image Distribution In Flash Memory

    6 Configuration Mode Introduction 6.5 MSPI there is no limit placed on the number of RECONFIG_N events. Using MULTI BOOT with Failsafe Golden Images To support remote ‘infield’ bitstream updates, Multiboot can include a failsafe Golden Image. We recommend this Golden (fallback) Image is always stored as the last bitstream in external Flash.

  • Page 78: Figure 6-45 Input The Start Address For The Next Bitstream

    Golden Image 0x2. SPI Flash Start Address When generating a bitstream using the GOWIN EDA tools, the user can specify the SPI Flash start address of the next bitstream to be loaded. Using the GOWIN EDA software, open the "Bitstream" option dialog box.

  • Page 79: Figure 6-46 Set The Programming Address For The External Flash

    Before configuring, set the MODE value of the 1 FPGA to be MSPI and the mode  value of the downstream FPGAs to be SERIAL. Gowin FPGA products do not support the configuration of one FPGA using multiple  Flash devices. UG290-2.5.2E...

  • Page 80: Mspi Configuration Timing

    6Configuration Mode Introduction 6.5MSPI Figure 6-47 Connection Diagram for Configuring Multiple FPGAs via Single Flash 6.5.5 MSPI Configuration Timing MSPI Download Timing is as shown in Figure 6-48. Figure 6-48 MSPI Download Timing UG290-2.5.2E 71(100)

  • Page 81: Dual Boot Configuration (Supported By Littlebee Family Only)

    6.6 DUAL BOOT Configuration (Supported by LittleBee® 6 Configuration Mode Introduction Family Only) Figure 6-16 shows the timing parameters. Table 6-16 MSPI Configuration Timing Parameters Name Description Min. Max. MCLK clock period 15ns mclkp MCLK clock high time 7.5ns mclkh MCLK clock low time 7.5ns mclkl...

  • Page 82: Figure 6-50 Dual Boot Flow Chart

     selected for the three attempts to start from external Flash. The startup address needs to be written to the bitstream through Gowin software in advance. If the configuration fails three times, the devices attempt to start from the built-in Flash.

  • Page 83: Cpu Mode

    Download DUAL BOOT Program for more details. 6.7 CPU Mode In CPU mode, the Host configures Gowin FPGA products through the 8-bit data bus interface. CPU mode pins are shown in Table 6-17. Table 6-17 CPU Mode Pins Pin Name...

  • Page 84: Configuration Timing

    Figure 6-52 CPU Mode Configuration Timing 6.8 SERIAL Mode In SERIAL mode, Host configures Gowin FPGA products via serial interface. SERIAL is one of the configuration modes that use the least number of pins. The SERIAL mode can only write bitstream data to FPGA and cannot readback data from FPGA devices;...

  • Page 85: Figure 6-53 Connection Diagram For Serial Mode

    6 Configuration Mode Introduction 6.8 SERIAL Mode cannot read information on the ID CODE and USER CODE and status register. A definition of the pins employed in the SERIAL mode is provided in Table 6-18. Table 6-18 Pin Definition in SERIAL Configuration Mode Pin Name Description I, internal...

  • Page 86: I 2 C Mode

    MUST be held inactive (pulled-up) during Autoboot, otherwise the device maynot be configured correctly. In I C Mode, Gowin FPGA products are configured by Host via I interface. I C Mode is one of the configuration modes that use the least number of pins.

  • Page 87: Figure 6-55 Connection Diagram For I 2 C Mode

    (1). Each frame in the message is followed by an ACK/NACK ACK/NACK bit bit, and Gowin FPGA returns 0 if correct. DATA Data A data has 8bits, and the most significant bit is sent first.
  • Page 88 If you use I C to write Flash, the bitstream file needs to be conveted into specific bitstream file first. The conversion tool is included in Gowin Programmer, and the name after conversion is suffixed with ". I2C ". Other than the power requirements, the following conditions need to...

  • Page 89: Process Of Gw1N-2 Configuring Or Programming Sram/Flash

    6 Configuration Mode Introduction 6.9 I2C Mode 6.9.1 Process of GW1N-2 Configuring or Programming SRAM/Flash The data stream file format for confgiuring SRAM is FS (.fs) or Binary (.bin), and the data stream file format for programming the internal Flash is I2C (.i2c).

  • Page 90: Bitstream File Configuration

    7Bitstream File Configuration 7.1Configuration Options Bitstream File Configuration The features of Gowin FPGA products need to be configured and programmed using Gowin software. The settings mainly include configuration pins multiplexing options and bitstream data configuration options. This chapter describes the bitstream file configuration. For the details about the configuration pin reuse, please refer to 5.1.2...

  • Page 91: Configuration Data Encryption (Supported By Arora Family Only)

    Figure 7-1 Configuration Options Note! The security bit setting is forcibly checked after Gowin software verifies the encryption key setting option. In addition to ensuring the data is secure during the transmission process, using these bitstream settings during configuration also prevents any readback, thereby ensuring maximum protection of user data.

  • Page 92: Enter Encryption Key

    Key. This operation is named as "lock" in this manual. When it's locked, all the read back data is 1. 7.2.2 Enter Encryption KEY Refer to the steps below to write the encryption keys in Gowin software: 1. Open the corresponding project in Gowin software;...

  • Page 93: Programming Operation

    Note! The initial value of the Gowin FPGA keys is 0. If a key value is changed to 1, it cannot be changed back to 0. For example, the key value written during an operation is 00000000-00000000-00000000-00000001, and the last bit of the modified key must be 1.

  • Page 94: Figure 7-4 Aes Security Configure

    7.2 Configuration Data Encryption (Supported by Arora 7 Bitstream File Configuration Family only) Figure 7-4 AES Security Configure This configuration contains the following three parts: Write: Write Key;  Read: Read Key;  Lock: Lock read and write access to the Key. ...

  • Page 95: Programming Flow

    7.2 Configuration Data Encryption (Supported by Arora 7 Bitstream File Configuration Family only) 7.2.5 Programming Flow Figure 7-5 ~ Figure 7-8 show the flow of how to program or lock the AES key. All the flows are based on JTAG protocol. Check ID CODE Check the device ID to determine whether the JTAG protocol works properly and whether the programing object is correct to avoid...

  • Page 96: Figure 7-6 Read Aes Key Flow

    7.2 Configuration Data Encryption (Supported by Arora 7 Bitstream File Configuration Family only) Read AES Key Figure 7-6 Read AES Key Flow Transmit ISC Enable Command (0x15) Transmit Read Key Command (0x25) Read 128 Bits Transmit ISC Disable Command (0x3A) Stop UG290-2.5.2E 87(98)

  • Page 97: Figure 7-7 Program Aes Key Flow

    7.2 Configuration Data Encryption (Supported by Arora 7 Bitstream File Configuration Family only) Program AES Key Figure 7-7 Program AES Key Flow Transmit ISC Enable Command (0x15) Transmit Program EFuse Command (0x24) Transmit Program Key Command (0x29) Transmit 128bits Delay 800 ms Transmit Read ID Command ( 0x11)

  • Page 98: Configuration File Size

    Stop 7.3 Configuration File Size The Gowin bitstream format can be Text (ASCII) with annotations or Binary with no annotations. The file with a .fs suffix is a text format file. Lines beginning with “//” are annotations. The others is the bitstream data.

  • Page 99: Figure 7-9 Bitstream Format Generation

    7 Bitstream File Configuration 7.3 Configuration File Size Figure 7-9 Bitstream Format generation Gowin supports compressing bitstream data. The compression ratio is related to the user design. This manual only provides uncompressed configuration file sizes, as shown in Table 7-1.

  • Page 100: Configuration File Loading Time

    If SPI Flash is used to store bitstream file, memory margin is required. 7.4 Configuration File Loading Time Gowin FPGA can be used as Master to read bitstream files from Flash and configure SRAM, including Autoboot mode and MSPI mode. In Autoboot mode, FPGA reads bitstream files from internal Flash.

  • Page 101: Table 7-2 Loading Frequency Of Config File

    7 Bitstream File Configuration 7.4 Configuration File Loading Time Table 7-2 Loading Frequency of Config File Max. Loading Frequency of Max. Loading Frequency of Device Autoboot MSPI GW2A-55/55C GW2A-18/18C – GW2AR-18/18C 125 MHz GW2ANR-18C GW1N-1 26 MHz GW1N-1S GW1NS-2 GW1NSR-2 GW1NS-2C 33 MHz GW1NSR-2C...

  • Page 102: Table 7-3 Loading Time In Mspi Mode

    7 Bitstream File Configuration 7.4 Configuration File Loading Time The bitstream file loading time in MSPI mode is as shown in Table 7-3. Table 7-3 Loading Time in MSPI Mode Loading Time Loading Time Loading Time Loading Time Max. Number (ms, when (ms, when (ms, when...

  • Page 103: Safety Precautions

    GOWINSEMI products have specific IDs that distinguish them from the other series of products. The bitstream generated by Gowin Software contains an ID verification directive, as such, users only need to select the specific device when creating a new project.
  • Page 104 Flash according to the configuration mode selected. (On-chip Flash is supported by the LittleBee® Family of FPGA products only.) If the data is loaded to the SRAM, Gowin software will set the security  bit automatically in the process of bitstream generation, and no user can read SRAMs.

  • Page 105: Boundary Scan

    To perform a boundary scan, follow the steps outlined below: 1. Connect the FPGA development board to the PC and then power up; 2. Open Gowin programmer and scan the connected devices; 3. Double-click in the "Operation" field and select "External Flash Mode”...

  • Page 106: Figure 9-1 Boundary Scan Operation Schematic Diagram

    9 Boundary Scan Figure 9-1 Boundary Scan Operation Schematic Diagram The boundary scan operation can only be performed on the external Flash of FPGA and cannot be used to program the embedded Flash or SRAM. This operation is irrelevant with the FPGA MODE value, but it is slower than that of the external Flash programming via JTAG.

  • Page 107: Spi Flash Selection

    0x0B Note! The Flash read instructions supported by Gowin FPGA must have at least one 03 or 0B. Use the regular reading instruction if the clock frequency is no higher than 30 MHz. Use the fast reading instruction if the clock frequency is higher than 30 MHz. Fast read requires the FASTRD_N pin to be pulled down, and the clock frequency cannot be higher than 70MHz.

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