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Summary of Contents for GOWIN UART Master IP
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Page 1: User Guide
Gowin UART Master and Slave IP User Guide IPUG511-1.4E, 09/29/2019... - Page 2 Copyright 2019 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. © No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI.
- Page 3 Revision Date Revision Description 12/20/2018 1.0E Initial version published. 03/28/2019 1.1E Supported products updated. 05/08/2019 1.2E Changed AXI interface to SRAM interface. 07/22/2019 1.3E Interface configuration added. UART Master released as an IP; UART Slave released as 09/29/2019 1.4E an open source reference design.
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Page 4: Table Of Contents
3.2 Gowin UART Slave IP ......................5 4 Working Principle .................... 6 4.1 System Diagram ......................... 6 4.2 Gowin UART Master IP Register ..................6 4.2.1 Receive Buffer Register (RBR) ..................7 4.2.2 Transmit Holding Register (THR) ..................7 4.2.3 Interrupt Enable Register (IER) ..................7 4.2.4 Interrupt Identification Register (IIR)................ -
Page 5: Contents
Contents 6 Reference Design ..................15 IPUG511-1.4E... -
Page 6: List Of Figures
List of Figures List of Figures Figure 4-1 System Diagram ....................... 6 Figure 4-2 Receive Buffer Register ....................7 Figure 4-3 Transmit Holding Register ....................7 Figure 4-4 Interrupt Enable Register....................8 Figure 4-5 Interrupt Identification Register ..................8 Figure 4-6 Line Control Register ......................9 Figure 4-7 Modem Control Register.................... - Page 7 Table3-1 SRAM Interface Signal Definition ..................4 Table3-2 UART Side Signal Definition ....................4 Table3-3 UART Slave Signal Definition ..................... 5 Table4-1 Gowin UART Master IP Register ..................7 Table4-2 Receive Buffer Register Bit Definition ................. 7 Table4-3 Transmit Holding Register Bit Definitions ................7 Table4-4 Interrupt Enable Register Bit Definition ................
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Page 8: About This Manual
GW2A series of FPGA products: GW2A-18, GW2A-55 GW2AR series of FPGA products: GW2AR-18 1.3 Related Documents The latest user guides are available on the Gowin website. Refer to the related documents at www.gowinsemi.com DS100, GW1N Series of FPGA Product Data Sheet ... -
Page 9: Technical Support And Feedback
Static Random Access Memory UART Universal Asynchronous Receiver/Transmitter 1.5 Technical Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. URL: www.gowinsemi.com... -
Page 10: Function Introduction
The Universal Asynchronous Receiver/Transmitter, commonly referred to as the UART, is an asynchronous transceiver. Gowin UART Master IP is a UART Master controller with synchronous SRAM interface, and the external connection standard RS-232 interfacE. Data is converted between serial communication and parallel communication. -
Page 11: Signal Definition
3Signal Definition 3.1Gowin UART Master IP Signal Definition 3.1 Gowin UART Master IP 3.1.1 SRAM Interface Signal Table3-1 SRAM Interface Signal Definition Signal name Description Remarks Working clock, rising edge I_CLK sampling I_RESETN Reset signal I_TX_EN Write enable signal SRAM write... -
Page 12: Gowin Uart Slave Ip
3Signal Definition 3.2Gowin UART Slave Signal name Description Remarks RTSn Request to send, low effective 3.2 Gowin UART Slave Table3-3 UART Slave Signal Definition Signal name Description Remarks SCLK Clock signal RSTN Reset signal Serial output signal Serial input signal... -
Page 13: Working Principle
The UART Master IP acts as a "bridge." The main controller transmits the command or data to the UART Master IP through synchronous SRAM interface, and then the UART Master IP is sent to the UART Slave through the UART; or uploads the UART Slave data to the main controller through synchronous SRAM interface shown in Figure 4-1. -
Page 14: Receive Buffer Register (Rbr)
4Working Principle 4.2Gowin UART Master IP Register Table4-1 Gowin UART Master IP Register Register name Register address Register bit width Types Description Receive Buffer 0x00 read Register Transmit Holding 0x00 write Register Interrupt Enable 0x01 write Register Interrupt 0x02 read... -
Page 15: Interrupt Identification Register (Iir)
4Working Principle 4.2Gowin UART Master IP Register Figure4-4 Interrupt Enable Register Reserved 0000 RLSI THRI RHRI Table4-4 Interrupt Enable Register Bit Definition Name Defaults Access type Description Reserved Reserved Modem status interrupt enable 0：Disable Modem status write interrupt ... -
Page 16: Line Control Register (Lcr)
4Working Principle 4.2Gowin UART Master IP Register Name Defaults Access type Description 1：No interruption waiting 4.2.5 Line Control Register (LCR) The line control register is shown in Figure4-6. The line control register contains the serial communication configuration bits as defined in Table4-6. -
Page 17: Line Status Register (Lsr)
4Working Principle 4.2Gowin UART Master IP Register Name Defaults Access type Description Request to send 1：Drive RTSn signal is write 0：Drive RTSn signal is high The data terminal is ready 1：Drive DTRn signal is write 0：Drive DTRn signal is high 4.2.7 Line Status Register (LSR) -
Page 18: Modem Status Register (Msr)
4Working Principle 4.2Gowin UART Master IP Register Name Defaults Access type Description It means that the received data does not have the correct even or odd number, which is inconsistent with the setting by the check selection bit. Overflow error... -
Page 19: Gowin Uart Slave Implementation
Read/write Change in CTSN after last MSR read. Note! The default value is X: indicates that this bit is driven by an external input signal. 4.3 Gowin UART Slave Implementation Figure4-10 UART Slave Implementation Block Diagram UART sclk Slave Parameter... -
Page 20: Interface Configuration
Interface Configuration Users can use the IP core generator tool in the IDE to call and configure Gowin UART MASTER IP. 5.1 UART MASTER IP Core Interface UART MASTER configuration interface is as shown in Figure5-1. Figure5-1 UART MASTER Configuration Interface... -
Page 21: Uart Slave Ip Core Interface
5.2UART SLAVE Reference Design Project 5.2 UART SLAVE Reference Design Project Open Gowin YunYuan software, click “File > Open” to open the “Open File” dialog box, select the project file (*.gprj), and then open the project, as shown in Figure5-2. - Page 22 6Reference Design Reference Design For more details, please refer to the UART reference design at Gowin official website. IPUG511-1.4E...
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