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Revision History Date Version Description 05/11/2018 1.06E Initial version published. For the QN88 and LQ144 packages, VCCX connects with 09/10/2018 1.07E VCCO7. LCDS pair added in Table 2-1. 11/20/2018 1.08E The EQ144 package added. Packages of devices embedded with PSRAM added. ...
Contents Contents Contents ....................... i List of Figures ..................... ii List of Tables ...................... iii 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Abbreviations and Terminology ................... 1 1.4 Support and Feedback ....................... 2 2 Overview ......................
List of Figures List of Figures Figure 2-1 GW2AR I/O Bank Distribution ..................8 Figure 3-1 View of GW2AR-18 QN88 Pins Distribution (Embedded with SDRAM) ......10 Figure 3-2 View of GW2AR-18 QN88P Pins Distribution (Embedded with PSRAM) ......11 Figure 3-3 View of GW2AR-18 QN88PF Pins Distribution (Embedded with PSRAM) ......
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List of Tables List of Tables Table 1-1 Abbreviations and Terminology ..................1 Table 2-1 Max. I/O Information and LVDS Pair .................. 4 Table 2-2 GW2AR Power Pin ......................4 Table 2-3 Quantity of GW2AR-18 Pins (Devices Embedded With SDRAM) ........5 Table 2-4 Quantity of GW2AR-18 Pins (Devices Embedded With PSRAM) ........
1.1 Purpose About This Guide 1.1 Purpose This manual contains an introduction to the GW2AR series of FPGA products together with a definition of the pins, a list of pin numbers, distribution of pins, and package diagrams. 1.2 Related Documents The latest user guides are available on GOWINSEMI Website.
1 About This Guide 1.4 Support and Feedback 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below.
2.1 PB-Free Package The GW2AR series of FPGA Products are PB free in line with the EU RoHS environmental directives. The substances used in the GW2AR series of FPGA products are in full compliance with the IPC-1752 standards.
2 Overview 2.2 Max. I/O Information and LVDS Pair 2.2 Max. I/O Information and LVDS Pair Table 2-1 Max. I/O Information and LVDS Pair Package Pitch (mm) Size (mm) E-pad Size(mm) GW2AR-18 – LQ144 20 x 20 120(35) EQ144 20 x 20 9.74 x 9.74 120(35) EQ144P...
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2 Overview 2.4 Pin Quantity GW2AR-18 Pin Type QN88P EQ144P QN88PF EQ144PF MODE1 MODE2 EXTR JTAGSEL_N Note! [1] Single end/Differential/LVDS I/O quantity include CLK pins, and download pins. [2] JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O.
2 Overview 2.5 Introduction to the I/O BANK 2.5 Introduction to the I/O BANK There are eight I/O Banks in the GW2AR series of FPGA products, as shown in Figure 2-1. Figure 2-1 GW2AR I/O Bank Distribution This manual provides an overview of the distribution view of the pins in the GW2AR series of FPGA products.
3 View of Pin Distribution 3.1 GW2AR-18 Pins Distribution View 3.1.1 View of QN88 Pins Distribution (Embedded with SDRAM) Figure 3-1 View of GW2AR-18 QN88 Pins Distribution (Embedded with SDRAM) Table 3-1 Other pins in GW2AR-18 QN88 (Embedded with SDRAM) 1, 22, 45, 66 VCCO0 VCCO1...
3 View of Pin Distribution 3.1 GW2AR-18 Pins Distribution View 3.1.2 View of QN88P Pins Distribution (Embedded with PSRAM) Figure 3-2 View of GW2AR-18 QN88P Pins Distribution (Embedded with PSRAM) Table 3-2 Other pins in GW2AR-18 QN88P (Embedded with PSRAM) 1, 22, 45, 66 VCCO0 VCCO2/VCCO7...
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3 View of Pin Distribution 3.1 GW2AR-18 Pins Distribution View EXTR MODE 87, 88 UG229-1.5E 12(26)
3 View of Pin Distribution 3.1 GW2AR-18 Pins Distribution View 3.1.3 View of QN88PF Pins Distribution (Embedded with PSRAM) Figure 3-3 View of GW2AR-18 QN88PF Pins Distribution (Embedded with PSRAM) Table 3-3 Other pins in GW2AR-18 QN88PF (Embedded with PSRAM) 1, 22, 45, 66 VCCO0 VCCO2...
3 View of Pin Distribution 3.1 GW2AR-18 Pins Distribution View 3.1.4 View of LQ144/EQ144 Pins Distribution (Embedded with SDRAM) Figure 3-4 GW2AR-18 LQ144/EQ144 Pins Distribution View (Embedded with SDRAM) Table 3-4 Other pins in GW2AR-18 LQ144/EQ144 (Embedded with SDRAM) VCC/VCCPLLL1 1, 36, 73, 108 VCCO0 VCCO1...
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3 View of Pin Distribution 3.1 GW2AR-18 Pins Distribution View 2, 17, 53, 74, 89, 107 EXTR MODE 142, 143, 144 UG229-1.5E 15(26)
3 View of Pin Distribution 3.1 GW2AR-18 Pins Distribution View 3.1.5 View of EQ144P Pins Distribution (Embedded with PSRAM) Figure 3-5 GW2AR-18 EQ144P Pins Distribution View (Embedded with PSRAM) Table 3-5 Other pins in GW2AR-18 EQ144P (Embedded with PSRAM) VCC/VCCPLLL1 1, 36, 73, 108 VCCO0 VCCO1...
3 View of Pin Distribution 3.1 GW2AR-18 Pins Distribution View 3.1.6 View of EQ144PF Pins Distribution (Embedded with PSRAM) Figure 3-6 GW2AR-18 EQ144PF Pins Distribution View (Embedded with PSRAM) Table 3-6 Other pins in GW2AR-18 EQ144PF (Embedded with PSRAM) VCC/VCCPLLL1 1, 36, 73, 108 VCCO0 VCCO1...
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3 View of Pin Distribution 3.1 GW2AR-18 Pins Distribution View EXTR MODE 142, 143, 144 UG229-1.5E 18(26)
3 View of Pin Distribution 3.1 GW2AR-18 Pins Distribution View 3.1.7 View of LQ176/EQ176 Pins Distribution (Embedded with SDRAM) Figure 3-7 GW2AR-18 LQ176/EQ176 Pins Distribution View (Embedded with SDRAM) Table 3-7 Other pins in GW2AR-18 LQ176/EQ176 (Embedded with SDRAM) 1, 44, 89, 132 VCCO0 155, 176 VCCO1...
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