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GW2A/GW2AR series of FPGA Products Schematic Manual
UG206-1.1E
GW2A/GW2AR series of FPGA Products
Introduction
using the GW2A/GW2AR series of FPGA products. This manual describes
the characteristics and special features of GW2A/GW2AR series FPGA
products and provides a comprehensive checklist to guide design
processes. The main contents of this guide are as follows:
Power Supply
core voltage (V
voltage (V
part of the chip, with a 2.5V or 3.3V power supply. If no V
OSC, and BSRAM circuits will be impacted and the chip will not be
functional.
www.gowinsemi.com
Users should follow a series of rules during circuit board design when
Power Supply
JTAG download
MSPI download
Clock pin
Difference pin
READY, RECONFIG_N, DONE
MODE
JTAGSEL_N
FASTRD_N
EXTR
Pin Multiplexing
Reference for the external crystal oscillator circuit
GW2AR Bank voltage
Supported configuration modes
Pin Distribution
1. Overview
Voltage types of the GW2A/GW2AR series of FPGA products include
), PLL voltage (V
CC
).
CCIO
V
is an auxiliary power supply that is used to connect the internal
CCX
2. Power Index
Users should ensure GOWINSEMI products are always used within
Schematic Manual
), auxiliary voltage (V
CCPLL
) and Bank
CCX
exists, I/O,
CCX
1(14)

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Summary of Contents for GOWIN GW2A Series

  • Page 1 GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.1E GW2A/GW2AR series of FPGA Products Schematic Manual Introduction Users should follow a series of rules during circuit board design when using the GW2A/GW2AR series of FPGA products. This manual describes the characteristics and special features of GW2A/GW2AR series FPGA products and provides a comprehensive checklist to guide design processes.
  • Page 2 GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.1E recommended operating conditions and range. Data beyond the working conditions and range are for reference only. GOWINSEMI does not guarantee that all devices will operate as expected beyond the standard operating conditions and range. Table 1 lists the recommended working range for each power voltage.
  • Page 3 GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.1E Figure 2 Isolate and Filter the V CCPLL V1P0 VCCPLL 4.7uF 100nF 10nF FB is a magnetic bead, reference model mh2029-221Y, ceramic capacitance 4.7uF, 100nF and 10nF. It offers an accuracy of more than ±...
  • Page 4 GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.1E MSPI Download 1. Overview As a master device, the MSPI configuration mode reads the configuration data automatically from the off-chip flash and sends it to the FPGA SRAM. 2. Signal Definition Table 4 Signal Definition for MSPI Configuration Mode Name Description MCLK...
  • Page 5 GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.1E Name Description clock No. LPLL_T_fb/RPLL_T_fb L/R PLL feedback the input pin, T(True) LPLL_C_fb/RPLL_C_fb I L/R PLL feedback the input pin, C(Comp) LPLL_T_in/RPLL_T_in L/R PLL clock input pin, T(True) LPLL_C_in/RPLL_C_in L/R PLL clock input pin, C(Comp) 3.
  • Page 6 GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.1E READY, the FPGA can configure only when the READY signal is high. The device should be restored by using the power on or triggering RECONFIG_N when the READY signal is low. As an output configuration pin, FPGA can be indicated for the current configuration state.
  • Page 7 GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.1E 3. Reference Circuit Figure 5 Reference Circuit VCCO3 4.7K 4.7K 4.7K READY RECONFIG_N DONE Note!  The upper pull power supply is the bank voltage value of the corresponding pin;  The resistance accuracy is not less than ± 5%. MODE 1.
  • Page 8 1. Overview Select the signal in JTAG mode. If the JTAG pin is set as GPIO in Gowin software, the JTAG pin is changed to GPIO pin after being powered on and successfully configured. The JTAG pin can be recovered by reducing the JTAGSEL_N.
  • Page 9 GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.1E FASTRD_N 1. Overview In MSPI configuration mode, signals are selected via reading the SPI flash speed rate. FASTRD_N is normal read mode if high level; FASTRD_N is high speed read mode if low level. Each manufacturer's flash high speed read instruction is different.
  • Page 10: Pin Multiplexing

    I/O after downloading the bitstream file. Configure pin multiplex via the Gowin software: a). Open the corresponding project in Gowin software; b). Select “Project > Configuration > Dual Purpose Pin” from the menu options, as shown in Figure 7;...
  • Page 11 GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.1E  READY: As a GPIO, READY can be used as an input or output. As an input GPIO for READY, the initial value of READY should be 1 before configuring. Otherwise, the FPGA will fail to configure; ...
  • Page 12 GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.1E GW2AR Bank Voltage Due to the SIP SDRAM is in the GW2AR, the BANK voltage connected with it will have a fixed value, which is as follows: 1. GW2AR-18 QN88 Package Table 11 GW2AR-18 QN88 Package Name Description Min.
  • Page 13 GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.1E Pin Distribution Before designing circuits, users should take the overall FPGA pin distribution needs into consideration and make informed decisions related to the application of the device architecture features, including I/O LOGIC, global clock resources, PLL resources, etc.
  • Page 14 GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.1E Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail: support@gowinsemi.com...
  • Page 15 Copyright©2018 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI. Disclaimer ™...

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