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GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual UG292-1.0E GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual Introduction You should follow some rules for circuit board design when using GW1NS & GW1NSR & GW1NSE & GW1NSER series of FPGA products. This manual describes the characteristics of GW1NS &...
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GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual UG292-1.0E There is no linear voltage regulator in devices of LX version, and V needs to be set to 1.8V. The I/O Bank voltage V can be set to 1.2 V, 1.5 V, or 1.8 V as required.
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GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual UG292-1.0E specific is as follows: Figure 1 Noise Processing V1P2 4.7uF FB is a magnetic bead, and the reference model is MH2029-221Y. The ceramic capacitance is 4.7uF, and It offers an accuracy of more than ±20%. JTAG Overview JTAG interface is used for downloading the bitstream to SRAM,...
GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual UG292-1.0E MSPI Overview FPGA as a master device, MSPI reads the data automatically from the off-chip flash then transmits it to the FPGA SRAM. Signal Description Table 3 Signal Description Name Description MCLK...
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GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual UG292-1.0E Signal Description Table 4 Signal Description Name Description Pins in global clock input, T(True), [x]: global clock GCLKT_[x] Pins for Global clock input, C(Comp), [x]: global GCLKC_[x] clock No.
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GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual UG292-1.0E I/O output standard Single/Differ Bank V Output Driver Strength (mA) SSTL25D_I Differential SSTL25D_II Differential SSTL33D_I Differential SSTL33D_II Differential SSTL18D_I Differential SSTL18D_II Differential HSTL18D_I Differential HSTL18D_II Differential HSTL15D_I Differential ...
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GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual UG292-1.0E Signal Description Table 6 Signal Description Name Description internal weak Low level pulse: start new GowinCONFIG RECONFIG_N pull-up configuration High-level pulse: device programmed and configured; READY Low-level pulse: The device cannot be programmed and configured, High-level pulse: Successfully programmed...
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Overview JTAGSEL_N is JTAG mode selection signal. If the JTAG pin is set to GPIO in Gowin software, the JTAG pin changes to GPIO after the device is powered on to configure successfully. If JTAG configuration fails, you can recover by pulling down JTAGSEL_N. If you do not set JTAG multiplexing, the JTAG configuration function is always available.
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After downloading bitstream files, it is used as general I/O. The steps are as follows: 1. Open the project in Gowin software; 2. Select "Project > Configuration > Dual Purpose Pin" from the menu, as shown in Figure 5;...
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GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual UG292-1.0E Figure 5 Configure Dual-purpose Pin Dual- purpose Pin SSPI: As a GPIO, SSPI can be used as input or output; MSPI: As a GPIO, MSPI can be used as input or output; ...
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GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual UG292-1.0E FPGA External Crystal Oscillator Circuit Reference Figure 6 FPGA External Crystal Oscillator Circuit VCC3P3 10nF CLK_G FB is a magnetic bead, and MH2029-221Y is the reference model. The resistance accuracy is not less than ±...
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GW1NSR-4C Table 17 GW1NSR -4 C Configuration Modes Configuration Modes JTAG AUTO BOOT √ √ MG64P MIPI GW1NS series of FPGA products support embedded MIPI interface modules. BANK0 of GW1NS-2 is MIPI input port and BANK2 is MIPI output www.gowinsemi.com.en...
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GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual UG292-1.0E port. BANK0/BANK1 of GW1NS-4 is MIPI input and BANK2 supports MIPI output. Note! For GW1NS-2C/2 devices of LX or UX version, V is set to 1.2V when BANK0 is CCO0 used as MIPI input and V is set to 1.2V when BANK2 is used as MIPI output.
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GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual UG292-1.0E Pinout Before the design of the circuit, you should take the FPGA pinout into consideration, and a reasonable choice should be made for IO LOGIC, global clock resource, PLL and differential signals, etc. Note! During the configuration, all I/O (except TCK) of the device is weak pull-up, and I/O status after configuration is controlled by user programs and constraints.
GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA Products Schematic Manual UG292-1.0E Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com...
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