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GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.9E GW2A/GW2AR series of FPGA Products Schematic Manual Introduction You should follow a series of rules for circuit board design when using the GW2A/GW2AR series of FPGA products. This manual describes the characteristics and special features of GW2A/GW2AR series of FPGA products and provides a comprehensive checklist to guide design processes.
GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.9E Power Supply Overview Voltage types of the GW2A/GW2AR series of FPGA products include core voltage (V ), PLL voltage (V ), auxiliary voltage (V ) and Bank CCPLL voltage (V is an auxiliary power supply that is used to connect the internal part of the chip, with a 2.5V or 3.3V power supply.
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GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.9E Power Filter Each FPGA power input pin is connected to the ground with a 0.1uF ceramic capacitor. The input end of the V core voltage should primarily conduct the noise processing. Specific reference is as shown in Figure 1. Figure 1 Noise Processing of the Input End of the V Core Voltage V1P0...
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GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.9E JTAG Circuit Reference Figure 3 JTAG Circuit Reference 4.7K VCC3P3 JTAG 0.1uF VCC3P3 I/O1 I/O4 I/O2 I/O3 SP3003_04XTG Note! The resistance accuracy is not less than 5%. The power supply of the 6th pin in the JTAG socket can be adjusted to VCC1P2, VCC1P5, VCC1P8 and VCC2P5 as required.
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GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.9E MSPI Circuit Reference Figure 4 MSPI Circuit Reference Note! 1K pull-down resistance is required for MCLK signal. The resistance accuracy is not less than 5%. Clock Pin Overview The clock pins include GCLK global clock pins and PLL clock pins. ...
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GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.9E Clock Input Selection If the external clock inputs as a PLL clock, the user is advised to input from the PLL dedicated pin. And the PLL_T end is selected if the external clock inputs from the single-end.
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GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.9E DONE, the DONE signal indicates that the FPGA is configured successfully. The signal is high after successful configuration. As an output configuration pin, FPGA can be indicated whether the current configuration is successful. If configured successfully, DONE is high, and the device enters into an operating state.
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GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.9E MODE Overview MODE spans the MODE0, MODE1, MODE2, and GowinCONFIG configuration MODE modes. When the FPGA powers on or a low pulse triggers the RECONFIG_N mode, the device enters the corresponding GowinCONFIG state according to the MODE value. MODE [2:0] is used to select the GowinCONFIG programming configuration mode.
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Overview Select the signal in JTAG mode. If the JTAG pin is set as GPIO in Gowin software, the JTAG pin is changed to GPIO pin after being powered on and successfully configured. The JTAG pin can be recovered by reducing the JTAGSEL_N.
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I/O after downloading the bitstream file. Configure pin multiplex via the Gowin Software: a). Open the corresponding project in Gowin Software. b). Select “Project > Configuration > Dual Purpose Pin” from the menu options, as shown in Figure 7.
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Please refer to PINOUT manual of the corresponding device for details. For the MODE value corresponding to different configuration modes, please refer to UG290, Gowin FPGA Products Programming and Configuration Guide. Note! If the Number of I/O ports are sufficient, use non-multiplexed pins first.
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GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.9E FB is a ferrite bead, with MH2029-221Y reference model, more than ± 5% resistance accuracy, and more than ± 10% capacitance accuracy. Bank Voltage For the detailed Bank voltage requirements, please refer to the following manuals.
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(0.5 x VCCO) or external reference voltage V using any I/O from the bank. For DDR pinout, please see TN662, Based on Gowin FPGA DDR2 & DDR3 Hardware Design Reference Manual. Note! During configuration, all GPIOs of the device are high-impedance with internal weak pull-ups.
GW2A/GW2AR series of FPGA Products Schematic Manual UG206-1.9E Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com...
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