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GOWIN GW1N Series User Manual

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DK_START_GW1N-LV4LQ144C6I5_V1.1
User Guide
DBUG353-1.06E, 01/06/2021

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Summary of Contents for GOWIN GW1N Series

  • Page 1 DK_START_GW1N-LV4LQ144C6I5_V1.1 User Guide DBUG353-1.06E, 01/06/2021...
  • Page 2 Copyright© 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI. Disclaimer ®...
  • Page 3 Revision History Date Version Description 6/13/2017 1.00E Initial version published. Precautions for using development board and selection 7/18/2017 1.01E range of MSPI download rate added. 11/20/2017 1.02E Notes for GW1N-1, GW1N-4/4B, and GW1N-9 updated. DK_START_GW1N-LV4LQ144C6I5_V1.1 circuit diagrams 8/29/2018 1.03E updated. ...

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................1 1.1 Purpose ..........................1 1.2 Supported Products ......................1 1.3 Related Documents ......................1 1.4 Abbreviations and Terminology ................... 2 1.5 Support and Feedback .......................
  • Page 5 3.8.1 Overview ........................16 3.8.2 GPIO Circuit ........................17 3.8.3 Pins Distribution ......................17 3.9 LVDS ..........................20 3.9.1 Overview ........................20 3.9.2 LVDS Circuit ........................20 3.9.3 Pins Distribution ......................20 4 Notes ......................23 5 Gowin Software ................... 25 DBUG353-1.06E...

  • Page 6: List Of Figures

    List of Figures List of Figures Figure 2-1 DK_START_GW1N-LV4LQ144C6I5_V1.1 ............... 3 Figure 2-2 A Development Board Kit ....................4 Figure 2-3 PCB Components ......................5 Figure 2-4 System Architecture ......................6 Figure 3-3 Connection Diagram for FPGA USB Downloading and Configuration ......10 Figure 3-4 Power System Distribution ....................
  • Page 7 List of Tables List of Tables Table 1-1 Abbreviations and Terminologies ..................2 Table 2-1 Development Board Specification ..................7 Table 3-3 FPGA Download and Pins Distribution ................11 Table 3-4 GW1N-4 FPGA Power Pins Distribution ................12 Table 3-5 FPGA Clock and Reset Pins Distribution ................14 Table 3-6 LED Pins Distribution ......................

  • Page 8: About This Guide

     Introduction to the use of the FPGA development software. 1.2 Supported Products The information in the guide applies to GW1N series of FPGA products: GW1N-4. 1.3 Related Documents The latest user guides are available on the GOWINSEMI Website. You can find the related documents at www.gowinsemi.com:...

  • Page 9: Abbreviations And Terminology

    Delay-locked Loop Digital Signal Processing LQ144 LQFP144 1.5 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail: support@gowinsemi.com...

  • Page 10: Development Board Description

    Figure 2-1 DK_START_GW1N-LV4LQ144C6I5_V1.1 The Development board adopts the GW1N-LV4/4BLQ144 devices of the GW1N series of FPGA products. It features a range of advanced features including low power consumption, instant start-up, high security, low-cost, and flexible extensions, all of which can effectively reduce the learning cost and help users quickly design and develop programmable logic devices.

  • Page 11: A Development Board Kit

    2Development Board Description 2.2A Development Board Kit slide switches, key switches, a clock, and LEDs, all of which are useful for both developers and hobbyists alike. With abundant GPIO resources, the development board can be used as the main board to design an image-sampling system and the other related systems by combining video daughter boards.

  • Page 12: Pcb Components

    2Development Board Description 2.3PCB Components 2.3 PCB Components Figure 2-3 PCB Components DBUG353-1.06E 5(25)

  • Page 13: System Architecture

    2Development Board Description 2.4System Architecture 2.4 System Architecture Figure 2-4 System Architecture FLASH 20PIN 20PIN MODE Configurat- LVDS LVDS Header Header External 40PIN GPIO Clock Header 40PIN GPIO DONE Header Light JTAG Reset Crystal Switch Oscillator 2.5 Features The structure and features of the development board are as follows: 1.

  • Page 14: Development Board Specification

    2Development Board Description 2.6Development Board Specification 5. LED  One power indicator (green)  One DONE indicator (green)  Four LEDs (green) 6. Memory  One 64Mbit SPI flash 7. GPIO  72 I/O Resources 8. LDO Power  Inverse voltage protection, overcurrent protection; ...
  • Page 15 2Development Board Description 2.6Development Board Specification Item Functional Description Technical Conditions Comments – LVDS LVDS, used for testing Ten pairs  USB interface ESD protection:  USB interface: ESD ± 15kV non-contact discharge, ± 8kV protection; contact discharge;   Power interface: Schottky diode is connected –...

  • Page 16: Fpga Circuits

    FPGA Circuits 3.1 FPGA Module Overview For the resources of GW1N series of FPGA Products, please refer to DS100, GW1N series of FPGA Products Data Sheet I/O BANK Introduction For the I/O BANK, package and pinout information, please refer to UG103, GW1N series of FPGA Products Package and Pinout 3.2 Download Interface...

  • Page 17: Usb Download Circuit

    3FPGA Circuits 3.2Download Interface 3.2.2 USB Download Circuit Figure 3-1 Connection Diagram for FPGA USB Downloading and Configuration USB_D+ USB_D- USB to JTAG Chip TDO_A MSPI_CK_A MSPI_CS_A Configure MSPI_DI_A FLASH MSPI_DO 3.2.3 Downloading the Data Stream The data stream file can be downloaded in the following ways: ...

  • Page 18: Pins Distribution

    3FPGA Circuits 3.3Power Supply 3.2.4 Pins Distribution Table 3-1 FPGA Download and Pins Distribution Signal Name Pin No. BANK Description JTAG Signal VCCO3 JTAG Signal VCCO3 JTAG Signal VCCO3 TDO_A JTAG Signal VCCO3 MSPI_CK_A FLASH signals configuration VCCO1 MSPI_CS_A FLASH signals configuration VCCO1 MSPI_DI_A FLASH signals configuration...

  • Page 19: Power System Distribution

    3FPGA Circuits 3.3Power Supply 3.3.2 Power System Distribution Figure 3-2 Power System Distribution 40PIN GPIO 5V 2A Power Adapter 40PIN GPIO VCCX (FPGA) Configure FLASH (W25Q64) TPS7A7001 3.3V 2A USB to JTAG （FT2232） VCCO0 (FPGA) TPS7A7001 Key&Switch 2.5V 2A VCCO1 (FPGA) VCCO2 (FPGA)

  • Page 20: Clock, Reset

    3FPGA Circuits 3.4Clock, Reset Note! The VCCO1 of GW1N-4 can only be supplied with 3.3V or 2.5V, optional. 3.4 Clock, Reset 3.4.1 Overview A 50MHz crystal oscillator is provided in the development board that connects to the PLL input pin. This can be employed as the input clock for the PLL in FPGA, and the output clock as needed via multiplication and division of the PLL frequency.

  • Page 21: Pins Distribution

    3FPGA Circuits 3.5LED 3.4.3 Pins Distribution Table 3-3 FPGA Clock and Reset Pins Distribution Signal Name Pin No. BANK Description 50MHz crystal oscillator FPGA_CLK 3.3V, 2.5V, 1.2V Input F_CLK_SMA External clock input 3.3V, 2.5V, 1.2V FPGA_RST_N Reset signal, active low 3.3V, 2.5V Note！...

  • Page 22: Switches

    3FPGA Circuits 3.6Switches Signal Name Pin No. BANK Description F_LED2 LED2 3.3V, 2.5V, 1.2V F_LED3 LED3 3.3V, 2.5V, 1.2V F_LED4 LED4 3.3V, 2.5V, 1.2V 3.6 Switches 3.6.1 Overview Four slide switches are incorporated into the development board. These are used to control input during testing. 3.6.2 Key Switch Circuit Figure 3-5 Key Switch Circuit VCCO2...

  • Page 23: Key

    3FPGA Circuits 3.7Key 3.7 Key 3.7.1 Overview Four key switches are embedded in the development board. Users can manually input a low level to the corresponding FPGA pins for testing purposes. 3.7.2 Key Circuit Figure 3-6 Key Circuit Diagram 3.7.3 Pins Distribution Table 3-6 Key Pins Distribution Signal Name Pin No.

  • Page 24: Gpio Circuit

    3FPGA Circuits 3.8GPIO 3.8.2 GPIO Circuit Figure 3-7 GPIO Circuit VCC3P3 VCC3P3 H_B_IO1 H_B_IO2 H_A_IO1 H_A_IO2 H_B_IO3 H_B_IO4 H_A_IO3 H_A_IO4 H_B_IO5 H_B_IO6 H_A_IO5 H_A_IO6 H_B_IO8 H_B_IO7 H_A_IO8 H_A_IO7 H_B_IO10 H_B_IO9 H_A_IO10 H_A_IO9 H_B_IO11 H_B_IO12 H_A_IO11 H_A_IO12 H_B_IO13 H_B_IO14 H_A_IO13 H_A_IO14 H_B_IO15 H_B_IO16 H_A_IO15...
  • Page 25 3FPGA Circuits 3.8GPIO Signal Name Pin No. 40P Socket Pin No. BANK Description H_A_IO5 General I/O VCCO0 H_A_IO6 General I/O VCCO0 H_A_IO7 General I/O VCCO0 H_A_IO8 General I/O VCCO0 H_A_IO9 General I/O VCCO0 H_A_IO10 General I/O VCCO0 H_A_IO11 General I/O VCCO0 H_A_IO12 General I/O...
  • Page 26 3FPGA Circuits 3.8GPIO Table 3-8 J9 FPGA Pin Distribution Signal Name Pin No. 40P Socket Pin No. BANK Description VCC3P3 3.3V H_B_IO1 General I/O VCCO0 H_B_IO2 General I/O VCCO0 H_B_IO3 General I/O VCCO0 H_B_IO4 General I/O VCCO0 H_B_IO5 General I/O VCCO0 H_B_IO6 General I/O...

  • Page 27: Lvds

    3FPGA Circuits 3.9LVDS Signal Name Pin No. 40P Socket Pin No. BANK Description H_B_IO33 General I/O VCCO1 H_B_IO34 General I/O VCCO1 H_B_IO35 General I/O VCCO1 H_B_IO36 General I/O VCCO1 VCC5 Note！ The VCCO1 of GW1N-4 can only be supplied with 3.3V or 2.5V, optional; 3.9 LVDS 3.9.1 Overview Two 2 mm DC3-20P sockets are reserved on the development board...
  • Page 28 3FPGA Circuits 3.9LVDS Signal Name Pin No. 40P Socket Pin No. BANK Description F_LVDS_A2_P Differential Channel 2+ 2.5V F_LVDS_A2_N Differential Channel 2- 2.5V F_LVDS_A3_P Differential Channel 3+ 2.5V F_LVDS_A3_N Differential Channel 3- 2.5V F_LVDS_A4_P Differential Channel 4+ 2.5V F_LVDS_A4_N Differential Channel 4- 2.5V F_LVDS_A5_P Differential Channel 5+...
  • Page 29 3FPGA Circuits 3.9LVDS Signal Name Pin No. 40P Socket Pin No. BANK Description F_LVDS_B5_N Differential Channel 5- 2.5V DBUG353-1.06E 22(25)

  • Page 30: Notes

    2. When downloading bitstream files to internal flash or external flash, set the MODE pin state to the correct configuration value, please refer to UG290, Gowin FPGA Products Programming and Configuration User Guide 3. 100 ohm terminating resistors are welded into the LVDS Port. As the output port, the corresponding terminating resistors are removed in the LVDS interface.
  • Page 31 4Notes 3.9LVDS  VCCO0, VCCO2, and VCCO3 can be set as 3.3V, 2.5V and 1.2V using jumpers.  The pins of J10 and J11 LVDS support TLVDS output/input test. DBUG353-1.06E 24(25)

  • Page 32: Gowin Software

    5 Gowin Software Gowin Software For the details, you can see SUG100, Gowin Software User Guide. DBUG353-1.06E 25(25)

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