Timing Mode Operation - HP E2466C User Manual

assigned to the master clock [(L↑) • (M = 0)] which clocks the PLD
information and the slave register outputs into the logic analyzer. The
"cqual#" (M = 0) signal from the PLD is used to qualify the master clock to
eliminate the collection of unnecessary data.
The logic analyzer master clock must always include the M=0 qualifier for the
transaction tracker to operate properly.
State Mode Buffered Signals
In state mode, most of the signals are latched by the bus clock before being
routed to the logic analyzer. The following signals, however, are always
buffered instead of latched:
APIC & JTAG groups
A20M#
FERR#
FLUSH#
IERR#
IGNNE#
INIT#
LINT0/INTR
LINT1/NMI
PREQ#
SMI#
STPCLK#

Timing Mode Operation

The HP E2466C acts as a buffer in timing mode. The buffer in the
preprocessor passes each Pentium II processor signal to the logic analyzer
regardless of the state of BCLK. The slave latch within the logic analyzer is
also bypassed and the PLD does not generate supplemental information. The
transaction tracker will not operate when the preprocessor is in timing mode.
Preprocessor Interface for the Pentium II Processor
Preprocessor Interface Hardware Reference
Modes of operation
3-7