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Reset Configuration Information
The following table describes the reset configuration information that
is displayed at reset.
Table 5. Reset Configuration
Signal at Reset
FLUSH#
INIT#
A8#
A9#
A10#
A7#
A6#
A5#
A[12:11]#
Figure 19
Reset Configuration
2-20
Configuration (asserted/deasserted)
Output Tristate Enabled/Disabled
Built-in Self Test Enabled/Disabled
AERR# Observation Policy Enabled/Disabled
BERR# Observation Policy Enabled/Disabled
BINIT# Observation Policy Enabled/Disabled
In-order Queue depth = 1/8
Power-on Reset Vector = 000FFFF0 or FFFFFFF0 hex
FRC Mode Enabled/Disabled
APIC Cluster ID (00, 01, 10, 11)
Preprocessor Interface for the Pentium II Processor
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