Disassembler Behavior; Physical Vs. Linear Addresses - HP E2466C User Manual

Using the Inverse Assembler
Analysis techniques
For hardware analysis, the State and Timing Waveform displays provide the
most relevant details. If these displays to not provide the level of detail
required for your analysis needs, you might need the restricted version of the
HP E2466C. Contact your HP Sales Office for information on obtaining the
appropriate Intel non-disclosure forms for the restricted version.

Disassembler Behavior

To display instruction disassembly, use a Pentium II processor run-control
tool such as the HP E3493A to enable Branch Trace Messages and disable the
processor instruction caches. Show "Branch Trace Messages" in the Filter
dialog, and select "Display Disassembly" in the Preferences dialog.
When a processor executes a branching instruction, the prefetch queues are
flushed, a Branch Trace Message (BTM) appears on the bus, and the
processor begins fetching code at the branch target address. The
disassembly software finds matching code reads between the current BTM
and the next matching BTM, reorders any out-of-order bursts, then
disassembles the code read data. In searching for code reads, any fetches
which are deferred are automatically paired with their corresponding
deferred replies to ensure that all code read data is found. This pairing is not
affected by the "Display Deferred Pairing" setting in the Preferences dialog.

Physical vs. Linear Addresses

Branch Trace Messages give linear causing and target addresses. The
addresses displayed for Memory Code Read transactions are physical. For
real-mode programs, this is not an issue since linear and physical addresses
are equivalent. For protected-mode programs with paging enabled, the
address bits higher than A[11] will usually be different. Linear addresses for
disassembled instructions are shown in the "IP Addr" column of the Listing
window.
Preprocessor Interface for the Pentium II Processor 2-19