Thz(Dq), Dq Out High Impedance Time From Ck/Ck# - Test Method Of Implementation; Signals Of Interest; Test Definition Notes From The Specification; Test References - Keysight Technologies D9020DDRC Manual

15 Data Strobe Timing (DST) Tests

tHZ(DQ), DQ Out HIGH Impedance Time From CK/CK# - Test Method of Implementation

The purpose of this test is to verify that the time when the DQ is no longer driving (from HIGH state
OR LOW state to the high impedance stage), to the clock signal crossing, is within the conformance
limits as specified in the JEDEC specification.

Signals of Interest

Mode Supported: DDR2, for LPDDR2 refer to the tHZ(DQ) Test (Low Power)
Signal cycle of interest: READ
Signal(s) of Interest:
•
•
Optional signal(s):
•
Signals required to perform the test on the oscilloscope:
•
•
•
•

Test Definition Notes from the Specification

Table 126 Timing Parameter By Speed Grade (DDR2-400 and DDR2-533) & (DDR2-667 and DDR2-800)
Parameter
Data-out high-impedance time from CK/CK
Parameter
Data-out high-impedance time from CK/CK
Table 127 Timing Parameter By Speed Grade (DDR2-1066)
Parameter
Data-out high-impedance time from CK/CK

Test References

See Table 41 - Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) and Table 42 -
Timing Parameters by Speed Grade (DDR2-667 and DDR2-800) in the JEDEC Standard JESD79-2E.
Also see Table 41 - Timing Parameters by Speed Grade (DDR2-1066) in the JESD208.
212
Data Signal (supported by Data Strobe Signal)
Clock Signal (CK as Reference Signal)
Chip Select Signal (this signal is used to separate DQ signals from different rank of memory)
Data Signal, DQ
Data Strobe Signal, DQS
Clock Signal, CK
Chip Select Signal, CS (optional)
Symbol
tHZ
Symbol
tHZ
Symbol
tHZ
DDR2-400
Min Max Min
x tAC max x
DDR2-667
Min Max Min
x tAC max x
DDR2-1066 Units
Min Max
x tAC max ps
DDR2(+LP) Compliance Testing Methods of Implementation
DDR2-533 Units Specific Notes
Max
tAC max ps 18
DDR2-800 Units Specific Notes
Max
tAC max ps 18, 40
Specific Notes
15,35