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Keysight Technologies D9020DDRC Manuals
Manuals and User Guides for Keysight Technologies D9020DDRC. We have
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Keysight Technologies D9020DDRC manual available for free PDF download: Manual
Keysight Technologies D9020DDRC Manual (370 pages)
DDR2(+LP) Compliance Test Application Methods of Implementation
Brand:
Keysight Technologies
| Category:
Test Equipment
| Size: 11 MB
Table of Contents
Table of Contents
11
Required Equipment and Software
6
In this Book
7
See also
8
Contact Keysight
9
Table of Contents
11
DDR2 -Quick Reference
19
DDR2(+LP) Compliance Test Application - at a Glance
21
Using Keysight License Manager
22
Phone or Fax
25
Installing the Software / 36
35
Installing the License Key
37
Using Keysight License Manager 5
37
2 Preparing to Take Measurements
41
Calibrating the Oscilloscope
42
Starting the DDR2(+LP) Compliance Test Application
43
Online Help Topics
45
Keysight D9020Ddrc Ddr2(+Lp) Compliance Test Application Compliance Testing Methods of Implementation 3 Measurement Clock Tests
47
3 Measurement Clock Tests
47
Probing for Measurement Clock Tests
48
Test Procedure
48
Clock Period Jitter - Tjit(Per) - Test Method of Implementation
50
Signals of Interest
50
Test Definition Notes from the Specification
50
Test References
50
Pass Condition
51
Measurement Algorithm
51
Cycle to Cycle Period Jitter - Tjit(CC) - Test Method of Implementation
52
Signals of Interest
52
Test Definition Notes from the Specification
52
Test References
53
Pass Condition
53
Measurement Algorithm
53
Cumulative Error - Terr(N Per) - Test Method of Implementation
54
Signals of Interest
54
Test Definition Notes from the Specification
54
Test References
55
Pass Condition
55
Measurement Algorithm
56
Cumulative Error (Across 13-50 Cycles) - Terr (13-50 Per) (Low Power) - Test Method of Implementation
57
Signals of Interest
57
Test Definition Notes from the Specification
57
Test References
57
Pass Condition
57
Measurement Algorithm
57
Average HIGH Pulse Width - Tch(Avg) - Test Method of Implementation
59
Signals of Interest
59
Test Definition Notes from the Specification
59
Test References
59
Pass Condition
59
Measurement Algorithm
60
Absolute HIGH Pulse Width - Tch(Abs) - Test Method of Implementation
61
Signals of Interest
61
Test Definition Notes from the Specification
61
Test References
61
Pass Condition
61
Measurement Algorithm
61
Average Low Pulse Width - Tcl(Avg) - Test Method of Implementation
62
Signals of Interest
62
Test Definition Notes from the Specification
62
Test References
62
Pass Condition
62
Measurement Algorithm
63
Absolute Low Pulse Width - Tcl(Abs) - Test Method of Implementation
64
Signals of Interest
64
Test Definition Notes from the Specification
64
Test References
64
Pass Condition
64
Measurement Algorithm
64
Half Period Jitter - Tjit(Duty) - Test Method of Implementation
65
Signals of Interest
65
Test Definition Notes from the Specification
65
Test References
65
Pass Condition
66
Measurement Algorithm
66
Average Clock Period - Tck(Avg) - Test Method of Implementation
67
Signals of Interest
67
Test Definition Notes from the Specification
67
Test References
67
Pass Condition
68
Measurement Algorithm
68
Absolute Clock Period - Tck(Abs) - Test Method of Implementation
69
Signals of Interest
69
Test Definition Notes from the Specification
69
Test References
69
Pass Condition
69
Measurement Algorithm
69
Single-Ended Signals AC Input Parameters Tests
71
Probing for Single-Ended Signals AC Input Parameters Tests
72
Test Procedure
72
VIH(AC) Test for DQ, DM - Test Method of Implementation
74
Signals of Interest
74
Test Definition Notes from the Specification
74
Test References
74
PASS Condition
75
Measurement Algorithm
75
VIH(AC) Test for DQS - Test Method of Implementation
76
Signals of Interest
76
Test Definition Notes from the Specification
76
Test References
76
PASS Condition
77
Measurement Algorithm
77
VIH(AC) Test for Address, Control - Test Method of Implementation
78
Signals of Interest
78
Test Definition Notes from the Specification
78
Test References
78
PASS Condition
79
Measurement Algorithm
79
VIH(DC) Test for DQ, DM - Test Method of Implementation
80
Signals of Interest
80
Test Definition Notes from the Specification
80
Test References
80
PASS Condition
81
Measurement Algorithm
81
VIH(DC) Test for DQS - Test Method of Implementation
82
Signals of Interest
82
Test Definition Notes from the Specification
82
Test References
82
PASS Condition
83
Measurement Algorithm
83
VIH(DC) Test for Address, Control - Test Method of Implementation
84
Signals of Interest
84
Test Definition Notes from the Specification
84
Test References
84
PASS Condition
85
Measurement Algorithm
85
VIL(AC) Test for DQ, DM - Test Method of Implementation
86
Signals of Interest
86
Test Definition Notes from the Specification
86
Test References
87
PASS Condition
87
Measurement Algorithm
87
VIL(AC) Test for DQS - Test Method of Implementation
88
Signals of Interest
88
Test Definition Notes from the Specification
88
Test References
89
PASS Condition
89
Measurement Algorithm
89
VIL(AC) Test for Address, Control - Test Method of Implementation
90
Signals of Interest
90
Test Definition Notes from the Specification
90
Test References
91
PASS Condition
91
Measurement Algorithm
91
VIL(DC) Test for DQ, DM - Test Method of Implementation
92
Signals of Interest
92
Test Definition Notes from the Specification
92
Test References
92
PASS Condition
93
Measurement Algorithm
93
VIL(DC) Test for DQS - Test Method of Implementation
94
Signals of Interest
94
Test Definition Notes from the Specification
94
Test References
94
PASS Condition
95
Measurement Algorithm
95
VIL(DC) Test for Address, Control - Test Method of Implementation
96
Signals of Interest
96
Test Definition Notes from the Specification
96
Test References
96
PASS Condition
97
Measurement Algorithm
97
Slewr Test for DQ, DM, DQS - Test Method of Implementation
98
Signals of Interest
98
Test Definition Notes from the Specification
98
Test References
99
PASS Condition
99
Measurement Algorithm
99
Slewr Test for Address, Control, Clock - Test Method of Implementation
100
Signals of Interest
100
Test Definition Notes from the Specification
100
Test References
101
PASS Condition
101
Measurement Algorithm
101
Slewf Test for DQ, DM, DQS - Test Method of Implementation
102
Signals of Interest
102
Test Definition Notes from the Specification
102
Test References
103
PASS Condition
103
Measurement Algorithm
103
Slewf Test for Address, Control, Clock - Test Method of Implementation
104
Signals of Interest
104
Test Definition Notes from the Specification
104
Test References
105
PASS Condition
105
Measurement Algorithm
105
Srqser (40Ohm) - Test Method of Implementation
106
Signals of Interest
106
Test Definition Notes from the Specification
106
Test References
106
PASS Condition
106
Measurement Algorithm
107
Srqsef (40Ohm) - Test Method of Implementation
108
Signals of Interest
108
Test Definition Notes from the Specification
108
Test References
108
PASS Condition
108
Measurement Algorithm
108
Srqser (60Ohm) - Test Method of Implementation
109
Signals of Interest
109
Test Definition Notes from the Specification
109
Test References
109
PASS Condition
109
Measurement Algorithm
109
Srqsef (60Ohm) - Test Method of Implementation
110
Signals of Interest
110
Test Definition Notes from the Specification
110
Test References
110
PASS Condition
110
Measurement Algorithm
110
VOH(AC) - Test Method of Implementation
111
Signals of Interest
111
Test Definition Notes from the Specification
111
Test References
111
PASS Condition
111
Measurement Algorithm
111
VOH(DC) - Test Method of Implementation
112
Signals of Interest
112
Test Definition Notes from the Specification
112
Test References
112
PASS Condition
112
Measurement Algorithm
112
VOL(AC) - Test Method of Implementation
113
Signals of Interest
113
Test Definition Notes from the Specification
113
Test References
113
PASS Condition
113
Measurement Algorithm
113
VOL(DC) - Test Method of Implementation
114
Signals of Interest
114
Test Definition Notes from the Specification
114
Test References
114
PASS Condition
114
Measurement Algorithm
114
5 Single-Ended Signals V /V
115
Probing for Single-Ended Signals VIH/VIL (Address, Control) Tests
116
(Address, Control) Tests
116
Test Procedure
116
VIHCA(AC) - Test Method of Implementation
118
Signals of Interest
118
Test Definition Notes from the Specification
118
Test References
118
PASS Condition
118
Measurement Algorithm
119
VIHCA(DC) - Test Method of Implementation
120
Signals of Interest
120
Test Definition Notes from the Specification
120
Test References
120
PASS Condition
120
Measurement Algorithm
120
VILCA(AC) - Test Method of Implementation
121
Signals of Interest
121
Test Definition Notes from the Specification
121
Test References
121
PASS Condition
121
Measurement Algorithm
121
VILCA(DC) - Test Method of Implementation
122
Signals of Interest
122
Test Definition Notes from the Specification
122
Test References
122
PASS Condition
122
Measurement Algorithm
122
6 Single-Ended Signals V /V
123
Probing for Single-Ended Signals VIH/VIL (Data, Mask) Tests
124
Test Procedure
124
6 Single-Ended Signals VIH/VIL
124
VIHDQ(AC) - Test Method of Implementation
126
Signals of Interest
126
Test Definition Notes from the Specification
126
Test References
126
PASS Condition
126
Measurement Algorithm
127
VIHDQ(DC) - Test Method of Implementation
128
Signals of Interest
128
Test Definition Notes from the Specification
128
Test References
128
PASS Condition
128
Measurement Algorithm
129
VILDQ(AC) - Test Method of Implementation
130
Signals of Interest
130
Test Definition Notes from the Specification
130
Test References
130
PASS Condition
130
Measurement Algorithm
131
VILDQ(DC) - Test Method of Implementation
132
Signals of Interest
132
Test Definition Notes from the Specification
132
Test References
132
PASS Condition
132
Measurement Algorithm
133
7 Single-Ended Signals AC Parameters Tests for Strobe Signals
135
Probing for Single-Ended Signals AC Parameter Tests for Strobe Signals
136
Test Procedure
136
VSEH(AC) (Strobe) - Test Method of Implementation
138
Signals of Interest
138
Test Definition Notes from the Specification
138
Test References
138
PASS Condition
138
Measurement Algorithm
139
VSEL(AC) (Strobe) - Test Method of Implementation
140
Signals of Interest
140
Test Definition Notes from the Specification
140
Test References
140
PASS Condition
140
Measurement Algorithm
140
8 Single-Ended Signals AC Parameters Tests for Clock
141
Probing for Single-Ended Signals AC Parameter Tests for Clock
142
Test Procedure
142
VSEH(AC) (Clock) - Test Method of Implementation
144
Signals of Interest
144
Test Definition Notes from the Specification
144
Test References
144
PASS Condition
144
Measurement Algorithm
145
VSEL(AC) (Clock) - Test Method of Implementation
146
Signals of Interest
146
Test Definition Notes from the Specification
146
Test References
146
PASS Condition
146
Measurement Algorithm
146
VIHCKE Test - Input Logic High (Clock Enable) - Test Method of Implementation
147
Measurement Algorithm
147
PASS Condition
147
Signals of Interest
147
Test Definition Notes from the Specification
147
Test References
147
VILCKE Test - Input Logic Low (Clock Enable) - Test Method of Implementation
148
Measurement Algorithm
148
PASS Condition
148
Signals of Interest
148
Test Definition Notes from the Specification
148
Test References
148
9 Single-Ended Signals Overshoot/Undershoot Tests
149
Probing for Overshoot/Undershoot Tests
150
Test Procedure
150
AC Overshoot Test Method of Implementation
152
Signals of Interest
152
Test Definition Notes from the Specification
152
Measurement Algorithm
154
PASS Condition
154
Test References
154
AC Undershoot Test Method of Implementation
155
Signals of Interest
155
Test Definition Notes from the Specification
155
Measurement Algorithm
157
PASS Condition
157
Test References
157
Differential Signals AC Input Parameters Tests
159
Probing for Differential Signals AC Input Parameters Tests
160
Test Procedure
160
Signals of Interest
162
Test Definition Notes from the Specification
162
VID(AC), AC Differential Input Voltage Test for DQS - Test Method of Implementation
162
Measurement Algorithm
163
PASS Condition
163
Test References
163
VID(AC), AC Differential Input Voltage Test for Clock - Test Method of Implementation
164
Signals of Interest
164
Test Definition Notes from the Specification
164
Test References
165
PASS Condition
165
Measurement Algorithm
165
VIX(AC), AC Differential Input Cross Point Voltage Test for DQS -Test Method of Implementation
166
Signals of Interest
166
Test Definition Notes from the Specification
166
Test References
167
PASS Condition
167
Measurement Algorithm
167
VIX(AC), AC Differential Input Cross Point Voltage Test for Clock -Test Method of Implementation
168
Signals of Interest
168
Test Definition Notes from the Specification
168
Test References
169
PASS Condition
169
Measurement Algorithm
169
Vihdiff(Ac) Test for DQS - Test Method of Implementation
170
Signals of Interest
170
Test Definition Notes from the Specification
170
Test References
170
PASS Condition
170
Measurement Algorithm
171
Vihdiff(Ac) Test for Clock - Test Method of Implementation
172
Signals of Interest
172
Test Definition Notes from the Specification
172
Test References
172
PASS Condition
172
Measurement Algorithm
173
Vihdiff(DC) Test for DQS - Test Method of Implementation
174
Signals of Interest
174
Test Definition Notes from the Specification
174
Test References
174
PASS Condition
174
Measurement Algorithm
175
Vihdiff(DC) Test for Clock - Test Method of Implementation
176
PASS Condition
176
Signals of Interest
176
Test Definition Notes from the Specification
176
Test References
176
Measurement Algorithm
177
Vildiff(Ac) Test for DQS - Test Method of Implementation
178
PASS Condition
178
Signals of Interest
178
Test Definition Notes from the Specification
178
Test References
178
Measurement Algorithm
179
Vildiff(Ac) Test for Clock - Test Method of Implementation
180
PASS Condition
180
Signals of Interest
180
Test Definition Notes from the Specification
180
Test References
180
Measurement Algorithm
181
Vildiff(DC) Test for DQS - Test Method of Implementation
182
PASS Condition
182
Signals of Interest
182
Test Definition Notes from the Specification
182
Test References
182
Measurement Algorithm
183
Vildiff(DC) Test for Clock - Test Method of Implementation
184
PASS Condition
184
Signals of Interest
184
Test Definition Notes from the Specification
184
Test References
184
Measurement Algorithm
185
11 Differential Signal AC Output Parameters Tests
188
Probing for Differential Signals AC Output Parameters Tests
188
Test Procedure
188
Signals of Interest
190
Test Definition Notes from the Specification
190
VOX , AC Differential Output Cross Point Voltage - Test Method of Implementation
190
Measurement Algorithm
191
PASS Condition
191
Test References
191
PASS Condition
192
Signals of Interest
192
Srqdiffr (40Ohm) - Test Method of Implementation
192
Test Definition Notes from the Specification
192
Test References
192
Measurement Algorithm
193
Measurement Algorithm
194
PASS Condition
194
Signals of Interest
194
Srqdifff (40Ohm) - Test Method of Implementation
194
Test Definition Notes from the Specification
194
Test References
194
Measurement Algorithm
195
PASS Condition
195
Signals of Interest
195
Srqdiffr (60Ohm) - Test Method of Implementation
195
Test Definition Notes from the Specification
195
Test References
195
Measurement Algorithm
196
PASS Condition
196
Signals of Interest
196
Srqdifff (60Ohm) - Test Method of Implementation
196
Test Definition Notes from the Specification
196
Test References
196
Measurement Algorithm
197
PASS Condition
197
Signals of Interest
197
Test Definition Notes from the Specification
197
Test References
197
Vohdiff(Ac) - Test Method of Implementation
197
Measurement Algorithm
198
PASS Condition
198
Signals of Interest
198
Test Definition Notes from the Specification
198
Test References
198
Voldiff(Ac) - Test Method of Implementation
198
12 Differential Signal Clock Cross Point Voltage Tests
199
Probing for Differential Signals Clock Cross Point Voltage Tests
200
Test Procedure
200
Measurement Algorithm
202
PASS Condition
202
Signals of Interest
202
Test Definition Notes from the Specification
202
Test References
202
VIXCA, Clock Cross Point Voltage - Test Method of Implementation
202
13 Differential Signals Strobe Cross Point Voltage Tests
203
Probing for Differential Signals Strobe Cross Point Voltage Tests
204
Test Procedure
204
Measurement Algorithm
206
PASS Condition
206
Signals of Interest
206
Test Definition Notes from the Specification
206
Test References
206
VIXDQ, Strobe Cross Point Voltage - Test Method of Implementation
206
Table of Contents
207
14 Clock Timing (CT) Tests
208
Probing for Clock Timing Tests
208
Test Procedure
208
Signals of Interest
210
Tac, DQ Output Access Time from CK/CK# - Test Method of Implementation
210
Test Definition Notes from the Specification
210
Test References
210
Measurement Algorithm
211
PASS Condition
211
Signals of Interest
212
Tdqsck, DQS Output Access Time from CK/CK #- Test Method of Implementation
212
Test Definition Notes from the Specification
212
Test References
212
Measurement Algorithm
213
PASS Condition
213
PASS Condition
214
Signals of Interest
214
Tdqsck (Low Power), DQS Output Access Time from Ck_T,Ck_C - Test Method of Implementation
214
Test Definition Notes from the Specification
214
Test References
214
Measurement Algorithm
215
Implementation
216
PASS Condition
216
Signals of Interest
216
Test Definition Notes from the Specification
216
Test References
216
Tdvac (Clock), Time above Vihdiff(Ac)/Below Vildiff(AC) - Test Method of Implementation
216
Measurement Algorithm
217
PASS Condition
218
Signals of Interest
218
Test Definition Notes from the Specification
218
Test References
218
Tqhs, Data Hold Skew Factor- Test Method of Implementation
218
Measurement Algorithm
219
PASS Condition
220
Signals of Interest
220
Tdqsckds Test - DQSCK Delta Short Test- Test Method of Implementation
220
Test Definition Notes from the Specification
220
Test References
220
Measurement Algorithm
221
PASS Condition
222
Signals of Interest
222
Tdqsckdm Test - DQSCK Delta Medium Test- Test Method of Implementation
222
Test Definition Notes from the Specification
222
Test References
222
Measurement Algorithm
223
Data Strobe Timing (Dst) Tests
225
Probing for Data Strobe Timing Tests
226
Test Procedure
226
Thz(Dq), DQ out HIGH Impedance Time from CK/CK# - Test Method of Implementation
228
Signals of Interest
228
Test Definition Notes from the Specification
228
Test References
228
Measurement Algorithm
229
PASS Condition
229
Tlz(Dqs), DQS Low-Impedance Time from CK/CK# - Test Method of Implementation
230
Tlz(Dq), DQ Low-Impedance Time from CK/CK# - Test Method of Implementation
232
Tdqsq, DQS-DQ Skew for DQS and Associated DQ Signals - Test Method of Implementation
234
Tqh, DQ/DQS Output Hold Time from DQS - Test Method of Implementation
236
Tdqss, DQS Latching Transition to Associated Clock Edge - Test Method of Implementation
238
Tdqsh, DQS Input HIGH Pulse Width - Test Method of Implementation
240
Tdqsl, DQS Input Low Pulse Width - Test Method of Implementation
242
Tdss, DQS Falling Edge to CK Setup Time - Test Method of Implementation
244
Tdsh, DQS Falling Edge Hold Time from CK - Test Method of Implementation
246
Twpst, Write Postamble - Test Method of Implementation
248
Twpre, Write Preamble - Test Method of Implementation
250
Trpre, Read Preamble - Test Method of Implementation
252
Trpst, Read Postamble - Test Method of Implementation
254
Thz(Dqs) Test (Low Power), DQS out HIGH Impedance Time from Clock - Test Method of Implementation
258
Tlz(Dq) Test (Low Power), DQ Low Impedance Time from Clock - Test Method of Implementation
262
Tqsh, DQS Output High Pulse Width - Test Method of Implementation
264
Tqsl, DQS Output Low Pulse Width - Test Method of Implementation
265
Tdqss Test (Low Power), DQS Latching Transition to Associated Clock Edge - Test Method of Implementation
266
Tdvac (Strobe), Time above Vihdiff(AC)/ below Vildiff(AC) - Test Method of Implementation
268
Keysight D9020Ddrc Ddr2(+Lp) Compliance Test Application Compliance Testing Methods of Implementation 16 Data Timing Tests
271
Probing for Data Timing Tests
272
Tds(Base), Differential DQ and DM Input Setup Time - Test Method of Implementation
275
Tdh(Base), Differential DQ and DM Input Hold Time - Test Method of Implementation
277
Tds(Derate), Differential DQ and DM Input Setup Time with Derating Support - Test Method of Implementation
279
Implementation
288
Tds1(Base), Single-Ended DQ and DM Input Setup Time - Test Method of Implementation
295
Tdh1(Base), Single-Ended DQ and DM Input Hold Time - Test Method of Implementation
297
Tvac (Data), Time above VIH(Ac)/Below VIL(AC) - Test Method of Implementation
305
Tdipw, DQ and DM Input Pulse Width - Test Method of Implementation
307
Tqhp, Data Half Period - Test Method of Implementation
308
Tds, DQ and DM Input Setup Time (Differential - VREF Based) - Test Method of Implementation
309
Tdh, DQ and DM Input Hold Time (Differential - VREF Based) - Test Method of Implementation
311
Table of Contents
313
Probing for Command Address Timing Tests
314
Tis(Base) - Address and Control Input Setup Time - Test Method of Implementation
316
Tih(Base) - Address and Control Input Hold Time - Test Method of Implementation
318
Tis(Derate), Address and Control Input Setup Time with Derating Support - Test Method of Implementation
320
Tvac (CS, CA), Time above VIH(Ac)/Below VIL(AC) - Test Method of Implementation
334
Tipw, Address and Control Input Pulse Width - Test Method of Implementation
336
Tiscke, CKE Input Setup Time - Test Method of Implementation
338
Tihcke, CKE Input Hold Time - Test Method of Implementation
339
Tisckeb, CKE Input Setup Time (Boot Parameter) - Test Method of Implementation
340
Tihckeb, CKE Input Hold Time (Boot Parameter) - Test Method of Implementation
341
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