Keysight Technologies D9020DDRC Manual page 306

Ddr2(+lp) compliance test application methods of implementation
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16
Data Timing Tests
Measurement Algorithm
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Acquire and split read and write burst of the acquired signal.
Take the first valid WRITE burst found.
Find all of the rising/falling DQ crossings at the V
tVAC(Data) is the time interval starting from a DQ rising V
following DQ falling V
IH(AC)
tVAC(Data) is also the time interval starting from a DQ falling V
the following DQ rising V
IL(AC)
Collect all tVAC(Data) results.
Determine the worst result from the set of tVAC(Data) measured.
Report the worst result from the set of tVAC(Data) measured. No compliance limit checking is
performed for this test. You need to manually check the test status (pass/fail) of this test based
on the worst tVAC(Data) and slew rate reported.
IH(AC)
crossing point.
crossing point.
DDR2(+LP) Compliance Testing Methods of Implementation
and V
levels in this burst.
IL(AC)
crossing point and ending at the
IH(AC)
crossing point and ending at
IL(AC)

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