Keysight Technologies D9020DDRC Manual page 32

Ddr2(+lp) compliance test application methods of implementation
Table of Contents

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Contents
tIS(base) - Address and Control Input Setup Time - Test Method of Implementation
tIH(base) - Address and Control Input Hold Time - Test Method of Implementation
tIS(derate), Address and Control Input Setup Time with Derating Support - Test Method of
Implementation
tIH(derate), Address and Control Input Hold Time with Derating Support - Test Method of
Implementation
tVAC (CS, CA), Time Above VIH(AC)/Below VIL(AC) - Test Method of Implementation
tIPW, Address and Control Input Pulse Width - Test Method of Implementation
32
300
Signals of Interest
Test Definition Notes from the Specification
300
301
Test References
301
PASS Condition
301
Measurement Algorithm
302
Signals of Interest
Test Definition Notes from the Specification
302
303
Test References
303
PASS Condition
303
Measurement Algorithm
304
304
Signals of Interest
Test Definition Notes from the Specification
309
Test References
310
PASS Condition
310
Measurement Algorithm
311
311
Signals of Interest
Test Definition Notes from the Specification
316
Test References
317
PASS Condition
317
Measurement Algorithm
318
Signals of Interest
Test Definition Notes from the Specification
318
Test References
318
PASS Condition
319
Measurement Algorithm
320
Signals of Interest
Test Definition Notes from the Specification
320
321
Test References
321
PASS Condition
321
Measurement Algorithm
300
302
304
311
318
320
DDR2(+LP) Compliance Testing Methods of Implementation
300
302
318
320

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Table of Contents