Holtek HT66F60A Manual page 152

• ADCR1 Register
Bit 7
Name —
R/W —
POR —
Bit 7 Unimplemented, read as "0"
Bit 6 VBGEN: Internal Bandgap voltage control
0: Disable
1: Enable
This bit controls the internal Bandgap circuit on/off function to the A/D converter.
When the bit is set high the bandgap voltage 1.25V can be used by the A/D converter.
If 1.25V is not used by the A/D converter and the LVR/LVD function is disabled then
the bandgap reference circuit will be automatically switched off to conserve power.
When 1.25V is switched on for use by the A/D converter, a time tBG should be
allowed for the bandgap circuit to stabilise before implementing an A/D conversion.
Bit 5 ADRFS: ADC Data Format Control
0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4
1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D data register section.
Bit 4 VREFS: Select ADC reference voltage
0: Internal ADC power
1: VREF pin
This bit is used to select the reference voltage for the A/D converter. If the bit is high,
then the A/D converter reference voltage is supplied on the external VREF pin. If the
pin is low, then the internal reference is used which is taken from the power supply pin
VDD.
Bit 3 Unimplemented, read as "0"
ADCK2, ADCK1, ADCK0: Select ADC clock source
Bit 2~0
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: Undefined
These three bits are used to select the clock source for the A/D converter.
Rev. 1.40
6 5 4
VBGEN �DRFS VREFS
R R/W R/W
1 1 0
SYS
/2
SYS
/4
SYS
/8
SYS
/16
SYS
/32
SYS
/64
SYS
15�
HT66F60A/HT66F70A
A/D Flash MCU with EEPROM
3 2 1
— �DCK� �DCK1
— R/W R/W
— 0 0
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0
�DCK0
R/W
0