Holtek HT66F60A Manual page 114

TMnDL Register
Bit 7
Name D�
R/W R
POR 0
Bit 7~0 TMnDL: TMn Counter Low Byte Register bit 7~bit 0
TMn 16-bit Counter bit 7~bit 0
TMnDH Register
Bit 7
Name D15
R/W R
POR 0
Bit 7~0 TMnDH: TMn Counter High Byte Register bit 7~bit 0
TMn 16-bit Counter bit 15~bit 8
TMnAL Register
Bit 7
Name D�
R/W R/W
POR 0
TMnAL: TMn CCRA Low Byte Register bit 7~bit 0
Bit 7~0
TMn 16-bit CCRA bit 7~bit 0
TMnAH Register
Bit 7
Name D15
R/W R/W
POR 0
TMnAH: TMn CCRA High Byte Register bit 7~bit 0
Bit 7~0
TMn 16-bit CCRA bit 15~bit 8
TMnRP Register
Bit 7
Name D�
R/W R/W
POR 0
TMnRP: TMn CCRP Register bit 7~bit 0
Bit 7~0
TMn CCRP 8-bit register, compared with the TMn Counter bit 15~bit 8.
Comparator P Match Period
0: 65536 TMn clocks
1~255: 256×(1~255) TMn clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter's highest eight bits. The result of this
comparison can be selected to clear the internal counter if the TnCCLR bit is set to
zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value.
Rev. 1.40
A/D Flash MCU with EEPROM
6 5 4
D6 D5 D4
R R R
0 0 0
6 5 4
D14 D13 D1�
R R R
0 0 0
6 5 4
D6 D5 D4
R/W R/W R/W
0 0 0
6 5 4
D14 D13 D1�
R/W R/W R/W
0 0 0
6 5 4
D6 D5 D4
R/W R/W R/W
0 0 0
114
HT66F60A/HT66F70A
3 2 1
D3 D� D1
R R R
0 0 0
3 2 1
D11 D10 D9
R R R
0 0 0
3 2 1
D3 D� D1
R/W R/W R/W
0 0 0
3 2 1
D11 D10 D9
R/W R/W R/W
0 0 0
3 2 1
D3 D� D1
R/W R/W R/W
0 0 0
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0
D0
R
0
0
D�
R
0
0
D0
R/W
0
0
D�
R/W
0
0
D0
R/W
0