Processor 3/6 - Clevo NH77DBQ Service Manual

Processor 3/6

5
NEAR CPU
1.05V_VCCST
R150 R516
100_04 56.2_1%_04
D
52 H_CPU_SVIDDAT
52 H_CPU_SVIDALRT#
52 H_CPU_SVIDCLK
R141
220_04
52 H_PROCHOT#
50 DDR_VTT_PG_CTRL
VCCST_PW RGD
R600 20_1%_04
32 H_PM_DOW N
TO PCH-H R621 *12.1_1%_04
32 PCH_PECI
TO EC
R622 *0402_short
45 H_PECI
C
32 PCH_THERMTRIP#
VCCST_PWRGD
B
R591
100K_04
R589 20K_04
28,31,45,52 ALL_SYS_PW RGD
C1032
*0.1u_10V_X7R_04
G
45 H_PROCHOT_EC
A
R592
100K_04
5
4 3
?
?
U37E
?
B31
35 PCH_CPU_BCLK_R_DP BCLKP
A32
35 PCH_CPU_BCLK_R_DN
BCLKN
D35
35 PCH_CPU_PCIBCLK_R_DP
PCI_BCLKP
C36
35 PCH_CPU_PCIBCLK_R_DN PCI_BCLKN
E31
35 CPU_24MHZ_R_DP
CLK24P
D31
35 CPU_24MHZ_R_DN
CLK24N
VIDALERT# BH31
VIDALERT#
BH32
VIDSCK
BH29
VIDSOUT
H_PROCHOT# BR30
R603 499_1%_04 PROCHOT#
PROCHOT#
BT13
DDR_VTT_CNTL
R578 60.4_1%_04 VCCST_PW RGD_CPU H13
VCCST_PWRGD
BT31
33 H_PW RGD
PROCPWRGD
BP35
32 PLTRST_CPU_N
RESET# PROC_TDO
BM34
32 H_PM_SYNC PM_SYNC PROC_TDI
PM_DOW N BP31
PM_DOWN PROC_TMS
PECI BT34
PECI PROC_TCK
J31
THERMTRIP#
PROC_TRST#
H_SKTOCC_N BR33
34,38 H_SKTOCC_N SKTOCC# PROC_PREQ#
BN1
PROC_SELECT# PROC_PRDY#
C302
*0.1u_10V_X7R_04 BM30
CATERR#
CFG_RCOMP
AT13
ZVM#
AW13
MSM#
AU13
RSVD1
AY13
RSVD2
5 OF 13
CML_H_IP_EXT/BGA
1.05V_VCCST
VDD3
R581
1K_04
VCCST_PW RGD
D
SYS_PW RGD# 2 G C1030
S Q58A
*0.1u_10V_X7R_04
D MTDK3S6R
5 G
S Q58B
MTDK3S6R
1.05DX_VCCSTG
H_PROCHOT#
R604 1K_04
Q59
C1039
2SK3018S3 47p_25V_NPO_02
CAD Note: Capacitor need to be placed
close to buffer output pin
4 3
2
Configuration Signals: The CFG signals have a
default value of '1' if not terminated on the board.
Refer to the appropriate platform design guide for
pull-down recommendations when a logic low is
desired.
CFG[0]: Stall reset sequence after PCU PLL
lock until de-asserted:
— 1 = (Default) Normal Operation; No
stall.
BN25 CFG0
T24
CFG_0 — 0 = Stall.
CFG_1
BN27
T23
CFG_1 CFG[1]: Reserved configuration lane.
BN26
CFG_2 CFG[2]: PCI Express* Static x16 Lane
BN28 CFG3
T22
CFG_3 Numbering Reversal.
BR20 CFG4 R587 1K_04
CFG_4
— 1 = Normal operation
BM20 CFG5
T25
CFG_5
— 0 = Lane numbers reversed.
BT20 CFG6
T97
CFG_6
BP20 CFG7 CFG[3]: Reserved configuration lane.
T26
CFG_7
BR23 CFG8
CFG[4]: eDP enable:
T95
CFG_8
BR22 CFG9 R582 *1K_04
— 1 = Disabled.
CFG_9
BT23
— 0 = Enabled.
CFG_10
BT22 CFG11
T96 CFG[6:5]: PCI Express* Bifurcation
CFG_11
BM19
— 00 = 1 x8, 2 x4 PCI Express*
CFG_12
BR19
CFG_13 — 01 = reserved
BP19 CFG14
T99
CFG_14 — 10 = 2 x8 PCI Express*
BT19 CFG15
T98
CFG_15
— 11 = 1 x16 PCI Express*
CFG[7]: PEG Training:
BN23
CFG_17
BP23 — 1 = (default) PEG Train immediately
CFG_16
BP22 following RESET# de assertion.
CFG_19
BN22
— 0 = PEG Wait for BIOS for training.
CFG_18
CFG[19:8]: Reserved configuration lanes.
BR27
BPM#_0
BT27
BPM#_1
BM31
BPM#_2
BT30
BPM#_3
BT28 H_TDO
H_TDO 33
BL32 H_TDI
H_TDI 33
BP28 H_TMS
H_TMS 33
H_TCK
BR28
H_TCK 33
BP30 H_TRST#
H_TRST# 38
BL30 H_PREQ#
H_PREQ# 38
BP27 H_PRDY#
H_PRDY# 38
BT25 CFG_RCOMP
R155
49.9_1%_04
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
CFG2
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
DISPLAY PORT PRESENCE STRAP
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
CFG4 0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
PCIE PORT BIFURCATION STRAPS
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG[6:5]
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
DEFENSIVE PULL DOWN SITE
1: (Default) PEG Train immediately following xxRESETB de assertion
CFG7
0: PEG Wait for BIOS for training
VCCIO 2,6,48
Title Title Title
[04]Processor 4/7-CLK/JTAG/MISC [04]Processor 4/7-CLK/JTAG/MISC [04]Processor 4/7-CLK/JTAG/MISC
3.3VA 30,31,32,33,36,38,44,48,53
1.05DX_VCCSTG 6,33,53
1.05V_VCCST 6,32,48,52
Size Size Size Document Number Document Number Document Number
VDD3 23,30,31,33,36,39,40,42,44,45,46,47,48,49,52,53,55,56,57,58,59,60,63,70,71,72
A3 A3 A3 SCHEMATIC1 SCHEMATIC1 SCHEMATIC1
Date: Date: Date: Tuesday, February 18, 2020 Tuesday, February 18, 2020 Tuesday, February 18, 2020
2
Schematic Diagrams
1
D
Sheet 4 of 67
1.05DX_VCCSTG
H_TMS
R624 51_04
H_TDI Processor 3/6
R146 51_04 C
H_TDO R562 100_04
H_TCK R623 51_04
3.3VA
H_SKTOCC_N
R599 100K_04
B
A
Rev Rev Rev
6-71-NH5D0-D02 6-71-NH5D0-D02 6-71-NH5D0-D02
D02 D02 D02
Sheet Sheet Sheet 4 4 4 of of of 74 74 74
1
Processor 3/6 B - 5