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Frame Buffer B
5
FRAME BUFFER PARTITION B 31..0
VRAM=K4G80325FB-HC03, HC28
M8A
NORMAL
FBB_D1
B4
DQ0_A
FBB_D6
A3
D
DQ1_A
FBB_D2
B3
DQ2_A
FBB_D4
B2
DQ3_A
FBB_D5
E3
DQ4_A
FBB_D3
E2
DQ5_A
FBB_D0
F2
DQ6_A
FBB_D7
G2
DQ7_A
FBB_EDC0
C2
EDC0_A
FBB_DBI0
D2
DBI0_A
FBB_W CK01
D4
WCK0_t_A
FBB_W CK01*
D5
WCK0_c_A
x16
x8
FBB_D13
B11
NC
DQ8_A
FBB_D14
A12
NC
DQ9_A
FBB_D12
B12
DQ10_A
NC
FBB_D11
B13
NC
DQ11_A
FBB_D15
E12
NC
DQ12_A
FBB_D8
E13
DQ13_A
NC
FBB_D9
F13
DQ14_A
NC
FBB_D10
G13
NC
DQ15_A
FBB_EDC1
C13
EDC1_A
GND
FBB_DBI1
D13
DBI1_A
NC
FBB_W CKB01
D11
WCK1_t_A
NC
FBB_W CKB01*
D10
C
WCK1_c_A
NC
U_MEM_SG_GDDR6
P/N =
Close to DRAM
FBVDDQ
FBVDDQ
FBVDDQ
C569
C572
C474
C637
C620
C627
Around DRAM
Around DRAM
FBVDDQ
FBVDDQ
C715
C678
C735
C742
C255
C716
B
FBVDDQ
FBVDDQ
C725
C705
C722
C643
C407
C625
C626
C617
C476
Right under DRAM
Right under DRAM
FBVDDQ
FBVDDQ
C480
C592
C729
C610
C408
C311
C277
C355
C409
C183
A
Close to DRAM
Close to DRAM
5
4
3
11
FBB_W CK01
11
FBB_W CK01*
11
FBB_W CK23
11
FBB_W CK23*
11
FBB_W CKB01
M8B
11
FBB_W CKB01*
11
FBB_W CKB23
NORMAL
11
FBB_W CKB23*
x16
x8
FBB_D24
U4
DQ0_B
NC
FBB_D30
V3
DQ1_B
NC
FBB_D29
U3
DQ2_B
NC
FBB_CMD0
H3
FBB_D31
U2
DQ3_B
NC
FBB_CMD9
G11
FBB_D25
P3
DQ4_B
NC
FBB_CMD8
G4
FBB_D26
P2
DQ5_B
NC
FBB_CMD32
H12
FBB_D27
N2
DQ6_B
NC
FBB_CMD7
H5
FBB_D28
M2
DQ7_B
NC
FBB_CMD11
H10
FBB_CMD15
J12
FBB_EDC3
T2
EDC0_B
GND
FBB_CMD14
J11
FBB_DBI3
R2
DBI0_B
NC
FBB_CMD3
J4
FBB_CMD1
J3
FBB_W CKB23
R4
WCK0_t_B
NC
FBB_CMD6
J5
FBB_W CKB23*
R5
WCK0_c_B
NC
FBB_CMD10
G10
FBB_D21
U11
DQ8_B
FBB_D16
V12
DQ9_B
FBB_D20
U12
DQ10_B
FBB_D17
U13
DQ11_B
FBB_D18
P12
DQ12_B
FBB_D22
P13
DQ13_B
FBB_D23
N13
DQ14_B
FBB_CMD4
L3
FBB_D19
M13
DQ15_B
FBB_CMD12
M11
FBB_CMD5
M4
FBB_EDC2
T13
EDC1_B
FBB_CMD13
L12
FBB_DBI2
R13
DBI1_B
FBB_CMD7
L5
FBB_CMD11
L10
FBB_W CK23
R11
WCK1_t_B
FBB_CMD15
K12
FBB_W CK23*
R10
WCK1_c_B
FBB_CMD14
K11
FBB_CMD3
K4
FBB_CMD1
K3
FBB_CMD6
K5
U_MEM_SG_GDDR6
FBB_CMD10
M10
P/N =
FBB_CMD2
J1
K10
11
FBB_CLK0*
J10
11
FBB_CLK0
C288
C405
C394
OPTION, Under DRAM
1V8_AON
C683
C701
C564
C586
C327
C727
C653
4
3
2
FBB_W CK01
FBB_DBI[3..0]
M8D
FBB_W CK01*
11
FBB_DBI[3..0]
FBB_W CK23
FBB_EDC[3..0]
FBB_W CK23*
11
FBB_EDC[3..0]
FBB_CMD[15..0]
FBB_W CKB01
11
FBB_CMD[15..0]
FBB_W CKB01*
FBB_CMD32
A11
VSS
11
FBB_CMD32
FBB_W CKB23
A13
FBB_D[31..0]
VSS
FBB_W CKB23*
11
FBB_D[31..0]
A2
VSS
A4
VSS
B1
M8C
VSS
B14
VSS
C10
VSS
C12
VSS
K1
FBB_VREFC
C3
CA0_A
VREFC
VSS
C5
CA1_A
VSS
D1
CA2_A
VSS
D12
CA3_A
VSS
D14
CA4_A
VSS
D3
CA5_A
VSS
E11
CA6_A
VSS
E4
CA7_A
VSS
F1
CA8_A
VSS
F12
CA9_A
VSS
F14
CABI_A
VSS
F3
CKE_A
VSS
G1
VSS
N5
SNN_FBBL_TCK_M
G12
TCK
VSS
T50
SNN_FBBL_TDI_M
F10
G14
TDI
VSS
T70
N10
SNN_FBBL_TDO_M
G3
TDO
T52
VSS
F5
SNN_FBBL_TMS_M
H11
TMS
VSS
T72
H4
VSS
L11
VSS
L4
CA0_B
VSS
M1
CA1_B
VSS
M12
CA2_B
VSS
M14
CA3_B
VSS
M3
CA4_B
VSS
N1
CA5_B
VSS
N12
CA6_B
VSS
N14
CA7_B
VSS
N3
CA8_B
VSS
P11
CA9_B
VSS
P4
CABI_B
VSS
R1
CKE_B
VSS
J14
FBB_ZQ_1_A
R12
ZQ_A
VSS
K14
FBB_ZQ_1_B
R14
ZQ_B
VSS
R3
VSS
T10
VSS
R296
R307
T12
VSS
T3
RESET
VSS
121_1%_04
121_1%_04
T5
VSS
U1
VSS
U14
VSS
V11
CLK_c
VSS
V13
CLK_t
VSS
V2
VSS
V4
VSS
SNN_FBBL_RFU_A_M
G5
RFU_A
T68
M5
SNN_FBBL_RFU_B_M
RFU_B
T57
U_MEM_SG_GDDR6
U_MEM_SG_GDDR6
P/N =
P/N =
FBVDDQ
R700
*549_1%_04
R290
1K_1%_04
G
12,17,23
GPIO10_FBVREF_SEL
10,12,13,15,17,18,20,21,22,23,24,25,56,59,60,72
11,12,13,15,16,17,18,19,25,59
Title
Title
Title
[14]MEMORY FBB 31..0
[14]MEMORY FBB 31..0
[14]MEMORY FBB 31..0
Size
Size
Size
Document Number
Document Number
Document Number
A3
A3
A3
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
6-71-NH5D0-D02
6-71-NH5D0-D02
6-71-NH5D0-D02
Date:
Date:
Date:
Friday, February 07, 2020
Friday, February 07, 2020
Friday, February 07, 2020
2
Schematic Diagrams
1
FBVDDQ
A1
VDD
A14
VDD
E10
VDD
E5
VDD
H13
VDD
H2
VDD
D
L13
VDD
L2
VDD
P10
VDD
P5
VDD
V1
VDD
V14
VDD
FBVDDQ
B10
VDDQ
B5
VDDQ
C1
VDDQ
C11
VDDQ
C14
VDDQ
C4
VDDQ
E1
VDDQ
E14
VDDQ
F11
VDDQ
Sheet 14 of 67
F4
VDDQ
H1
VDDQ
H14
VDDQ
J13
VDDQ
Frame Buffer B
J2
VDDQ
K13
VDDQ
K2
VDDQ
L1
VDDQ
C
L14
VDDQ
N11
VDDQ
N4
VDDQ
P1
VDDQ
P14
VDDQ
T1
VDDQ
T11
VDDQ
T14
VDDQ
T4
VDDQ
U10
VDDQ
U5
VDDQ
1V8_AON
A10
VPP
A5
VPP
V10
VPP
V5
VPP
B
FBB_VREFC
FBB_VREFC
15
R703
C1110
*931_1%_04
*820p_50V_X7R_04
Q69
*MTN2002ZS3
A
1V8_AON
FBVDDQ
Rev
Rev
Rev
D02
D02
D02
Sheet
Sheet
Sheet
14
14
14
of
of
of
74
74
74
1
Frame Buffer B B - 15
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