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PCH 9/9
5
NO REBOOThis signal has an integrated weak
BOOT STARP
pull-down resistor (20 KΩ nominal) to
This signal has an integrated weak
disable the no reboot strap functionality
pull-down resistor (20 KΩ nominal)
by default.
to default boot from SPI.
To enable no reboot on TCO Timer
To enable boot to LPC, this signal
expiration, this signal should be
should be pulled up to V3.3S through
pulled-up to V3.3S through a 1k to 2.2 KΩ
a 1k to 2.2 KΩ ±5% resistor.
±5% resistor.
3.3VA
3.3VS
R278
D
R689
*4.7K_04
*4.7K_04
LPSS_GSPI1_MOSI
LPSS_GSPI0_MOSI
3.3VS
GPIO
H: W / TPM
R260
L: W/O TPM
10K_04
BIOS
TPM
TPM_DET
R261
100K_04
W /O TPM
3.3VS
C
Leakage
*10K_04
R649
SMI#_R
PCH1.8VA
R629
DEBUG
10K_04
TX -> D+
R279
RX -> D-
R270
D02_102518_Alex_Typec DP issue
GPP_J1
R283
69
SMC_7411
R265
69
SMD_7411
R268
43
I2C_SCL_TP
R276
43
I2C_SDA_TP
PCH1.8VA
56,59
I2C2_SDA
56,59
I2C2_SCL
XTAL SELECT-1
HIGH -> 24 MHZ
LOW -> 38.4 MHZ
R207
B
4.7K_04
*10K_04
3.3VS
NH77
10K_04
CNVI_BRI_DT
*10K_04
3.3VS
D01A for CNVI samuel
10K_04
R208
*10K_04
4,34
PCH1.8VA PCH1.8VA
40
PCH1.8VA
M.2 CNVI STRAP
R616
R631
HIGH -> DISABLE
LOW -> ENABLE
20K_04
20K_04
40
R211
40
CNVI_BRI_RSP
40
100K_04
40
CNVI_RGI_RSP
40
CNVI_MFUART2_RXD
A
40
CNVI_MFUART2_TXD
CNVI_RGI_DT
R212
*100K_04
D01A for CNVI samuel
5
4
3
?
?
U43J
?
Y14
RSVD7
Y15
RSVD8
U37
RSVD6
U35
RSVD5
N32
RSVD3
R32
RSVD4
AH15
RSVD2
AH14
RSVD1
AL2
PREQ#
AM5
PRDY#
AM4
CPU_TRST#
AK3
PCH_2_CPU_TRIGGER_R
TRIGGER_OUT
AK2
TRIGGER_IN
10 OF 13
CML_PCH_H_IP_EXT/BGA
?
?
?
U43K
?
LPSS_GSPI1_MOSI
BA26
GPP_B22/GSPI1_MOSI
BD30
GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
GPP_B21/GSPI1_MISO
AU26
GPP_D10/ISH_SPI_CLK/GSPI2_CLK
GPP_B20/GSPI1_CLK
AW26
GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO
GPP_B19/GSPI1_CS0#
GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
LPSS_GSPI0_MOSI
BE30
GPP_B18/GSPI0_MOSI
BD29
GPP_B17/GSPI0_MISO
GPP_D16/ISH_UART0_CTS#/CNV_WCEN
BF29
GPP_B16/GSPI0_CLK
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
BB26
GPP_B15/GSPI0_CS0#
GPP_D14/ISH_UART0_TXD/I2C2_SCL
D02_1109_Alex
GPP_D13/ISH_UART0_RXD/I2C2_SDA
BB24
GPP_C9/UART0A_TXD
BE23
GPP_C8/UART0A_RXD
AP24
GPP_C11/UART0A_CTS#
BA24
GPP_C10/UART0A_RTS#
BD21
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_H20/ISH_I2C0_SCL
AW24
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_H19/ISH_I2C0_SDA
AP21
GPP_C13/UART1_TXD/ISH_UART1_TXD
AU24
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA
DEL ASM_SMI#
AV21
GPP_C23/UART2_CTS#
AW21
GPP_C22/UART2_RTS#
*0_06
UART2_TXD
BE20
GPP_C21/UART2_TXD
UART2_RXD
*0_06
BD20
GPP_C20/UART2_RXD
*0402_short
SMC_7411_I2C
BE21
GPP_C19/I2C1_SCL
*0402_short
SMD_7411_I2C
BF21
GPP_C18/I2C1_SDA
BC22
GPP_C17/I2C0_SCL
BF23
*0402_short
GPP_C16/I2C0_SDA
*0402_short
BE15
GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4/BK4
BE14
GPP_D23/ISH_I2C2_SCL/I2C3_SCL
CML_PCH_H_IP_EXT/BGA
?
11 OF 13
?
?
U43M
R259
BIOS
?
CNV_WR_CLKN
R258
BOARD_ID1
AW13
GPP_G0/SD_CMD
CNV_WR_CLKP
BOARD_ID2
R657
BE9
GPP_G1/SD_DATA0
TPM_DET
BF8
GPP_G2/SD_DATA1
CNV_WR_D0N
R662
BF9
24
GPIO4_1V8_MAIN_EN_R
GPP_G3/SD_DATA2
CNV_WR_D0P
BG8
GPP_G4/SD_DATA3
CNV_WR_D1N
SMI#_R
BE8
GPP_G5/SD_CD#
CNV_WR_D1P
BD8
GPP_G6/SD_CLK
AV13
GPP_G7/SD_WP
CNV_WT_CLKN
CNV_WT_CLKP
10K_04
R228
AP3
H_SKTOCC_N
GPP_I11/M2_SKT2_CFG0
AP2
GPP_I12/M2_SKT2_CFG1
CNV_WT_D0N
AN4
GPP_I13/M2_SKT2_CFG2
CNV_WT_D0P
AM7
GPP_I14/M2_SKT2_CFG3
CNV_WT_D1N
CNV_WT_D1P
AV6
CNVI_GNSS_PA_BLANKING
GPP_J0/CNV_PA_BLANKING
CNV_WT_RCOMP
AY3
48,53
GPP_J1
GPP_J1/CPU_C10_GATE#
75K_1%_04
R248
AR13
GPP_J11/A4WP_PRESENT
PCIE_RCOMPN
AV7
GPP_J10
PCIE_RCOMPP
100K_04
R630
AW3
GPP_J2
SD_1P8_RCOMP
AT10
100K_04
R237
GPP_J3
SD_3P3_RCOMP
22_04
R615
AV4
CNVI_BRI_DT
GPP_J4/CNV_BRI_DT/UART0B_RTS#
GPPJ_RCOMP_1P81
AY2
GPP_J5/CNV_BRI_RSP/UART0B_RXD
GPPJ_RCOMP_1P82
22_04
R627
BA4
CNVI_RGI_DT
GPP_J6/CNV_RGI_DT/UART0B_TXD
GPPJ_RCOMP_1P83
AV3
GPP_J7/CNV_RGI_RSP/UART0B_CTS#
AW2
GPP_J8/CNV_MFUART2_RXD
AU9
GPP_J9/CNV_MFUART2_TXD
13 OF 13
CML_PCH_H_IP_EXT/BGA
?
4,23,30,31,33,36,39,40,42,44,45,46,47,48,49,52,53,55,56,57,58,59,60,63,70,71,72
8,9,23,24,27,28,29,30,31,32,33,34,35,39,40,42,43,44,45,47,48,52,59,70,71
4
3
2
H_PREQ#
4
H_PRDY#
4
H_TRST#
4
R635
30.1_1%_04
PCH_2_CPU_TRIGGER
6
CPU_2_PCH_TRIGGER
6
BA20
BB20
BB16
AN18
BF14
AR18
BF17
BE17
AG45
AH46
AH47
AH48
DGPU_PW M_SELECT#
AV34
T64
GPP_A23/ISH_GP5
AW32
GPP_A22/ISH_GP4
SATA_PW R_EN
43
BA33
3G_CONFIG2
T63
GPP_A21/ISH_GP3
BE34
GPP_A20/ISH_GP2
BD34
GPP_A19/ISH_GP1
BF35
SB_BLON
Raven add 0731
GPP_A18/ISH_GP0
SB_BLON
28
BD38
BIOS
BD4
CNVI_W GR_CLKN
40
BE3
CNVI_W GR_CLKP
40
BB3
CNVI_W GR_D0N
40
BB4
CNVI_W GR_D0P
40
BA3
CNVI_W GR_D1N
40
BA2
CNVI_W GR_D1P
40
BC5
CNVI_W T_CLKN
40
BB6
CNVI_W T_CLKP
40
BE6
CNVI_W T_D0N
40
BD7
CNVI_W T_D0P
40
BG6
CNVI_W T_D1N
40
BF6
CNVI_W T_D1P
40
BA1
CNV_W T_RCOMP
150_1%_04
R628
Differential between RCOMPN/RCOMPP.
B12
PCIECOMP_N
100_1%_04
R665
Length matched to less than 1% trace.
PCIECOMP_P
A13
SD3_RCOMP_1P8
BE5
200_1%_04
R625
BE4
SD3_RCOMP_3P3
200_1%_04
R223
BD1
GPPJ_RCOMP_1P8
BE1
BE2
200_1%_04
R626
Y35
RSVD2
Y36
RSVD3
BC1
RSVD1
AL35
T71
TP
Title
Title
Title
[38] PCH 10_11/12-UART/I2C/GPIO
[38] PCH 10_11/12-UART/I2C/GPIO
[38] PCH 10_11/12-UART/I2C/GPIO
4,30,31,32,33,36,44,48,53
3.3VA
VDD3
Size
Size
Size
Document Number
Document Number
Document Number
3.3VS
A3
A3
A3
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
36
PCH1.8VA
Date:
Date:
Date:
Friday, February 07, 2020
Friday, February 07, 2020
Friday, February 07, 2020
2
Schematic Diagrams
1
D
Sheet 38 of 67
PCH 9/9
C
B
A
Rev
Rev
Rev
6-71-NH5D0-D02
6-71-NH5D0-D02
6-71-NH5D0-D02
D02
D02
D02
Sheet
Sheet
Sheet
38
38
38
of
of
of
74
74
74
1
PCH 9/9 B - 39
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