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Schematic Diagrams
Frame Buffer C
FRAME BUFFER PARTITION C 31..0
VRAM=K4G80325FB-HC03, HC28
D
Sheet 17 of 67
Frame Buffer C
C
Close to DRAM
C585
Around DRAM
C216
B
FBVDDQ
C717
Right under DRAM
FBVDDQ
A
C180
B - 18 Frame Buffer C
5
4
M10A
NORMAL
FBC_D1
B4
DQ0_A
FBC_D7
A3
FBC_D25
DQ1_A
FBC_D5
B3
FBC_D29
DQ2_A
FBC_D4
B2
FBC_D28
DQ3_A
FBC_D6
FBC_D31
E3
DQ4_A
FBC_D3
E2
FBC_D26
DQ5_A
FBC_D0
F2
FBC_D24
DQ6_A
FBC_D2
G2
FBC_D30
DQ7_A
FBC_D27
FBC_EDC0
C2
EDC0_A
FBC_DBI0
D2
FBC_EDC3
DBI0_A
FBC_DBI3
FBC_W CK01
D4
WCK0_t_A
FBC_W CK01*
D5
FBC_W CKB23
WCK0_c_A
FBC_W CKB23*
FBC_D23
x16
x8
FBC_D14
FBC_D20
B11
NC
DQ8_A
FBC_D15
A12
FBC_D22
DQ9_A
NC
FBC_D8
B12
FBC_D21
NC
DQ10_A
FBC_D12
FBC_D18
B13
NC
DQ11_A
FBC_D13
FBC_D19
E12
NC
DQ12_A
FBC_D9
E13
FBC_D17
DQ13_A
NC
FBC_D11
F13
FBC_D16
DQ14_A
NC
FBC_D10
G13
NC
DQ15_A
FBC_EDC2
FBC_EDC1
C13
FBC_DBI2
EDC1_A
GND
FBC_DBI1
D13
DBI1_A
NC
FBC_W CK23
FBC_W CKB01
FBC_W CK23*
D11
WCK1_t_A
NC
FBC_W CKB01*
D10
WCK1_c_A
NC
U_MEM_SG_GDDR6
P/N =
FBVDDQ
FBVDDQ
FBVDDQ
C469
C662
C629
C704
C470
Around DRAM
FBVDDQ
FBVDDQ
C706
C652
C690
C728
C695
FBVDDQ
C710
C723
C639
C642
C721
C746
C720
C714
C713
C641
C181
Right under DRAM
FBVDDQ
C187
C186
C185
C699
C638
C686
C673
C712
C663
C640
C700
Close to DRAM
Close to DRAM
5
4
3
FBC_W CK01
16
FBC_W CK01
FBC_W CK01*
16
FBC_W CK01*
FBC_W CK23
16
FBC_W CK23
FBC_W CK23*
16
FBC_W CK23*
FBC_W CKB01
16
FBC_W CKB01
FBC_W CKB01*
M10B
16
FBC_W CKB01*
FBC_W CKB23
16
FBC_W CKB23
FBC_W CKB23*
NORMAL
16
FBC_W CKB23*
x16
x8
M10C
U4
DQ0_B
NC
V3
DQ1_B
NC
U3
DQ2_B
NC
FBC_CMD0
H3
CA0_A
U2
DQ3_B
NC
FBC_CMD9
G11
P3
CA1_A
DQ4_B
NC
FBC_CMD8
G4
P2
CA2_A
DQ5_B
NC
FBC_CMD32
H12
CA3_A
N2
DQ6_B
NC
FBC_CMD7
H5
CA4_A
M2
DQ7_B
NC
FBC_CMD11
H10
CA5_A
FBC_CMD15
J12
T2
CA6_A
EDC0_B
GND
FBC_CMD14
J11
CA7_A
R2
DBI0_B
NC
FBC_CMD3
J4
CA8_A
FBC_CMD1
J3
R4
CA9_A
WCK0_t_B
NC
FBC_CMD6
J5
R5
CABI_A
WCK0_c_B
NC
FBC_CMD10
G10
CKE_A
U11
DQ8_B
V12
DQ9_B
U12
DQ10_B
U13
DQ11_B
P12
DQ12_B
P13
DQ13_B
N13
DQ14_B
FBC_CMD4
L3
M13
CA0_B
DQ15_B
FBC_CMD12
M11
CA1_B
FBC_CMD5
M4
CA2_B
T13
EDC1_B
FBC_CMD13
L12
R13
CA3_B
DBI1_B
FBC_CMD7
L5
CA4_B
FBC_CMD11
L10
CA5_B
R11
WCK1_t_B
FBC_CMD15
K12
CA6_B
R10
WCK1_c_B
FBC_CMD14
K11
CA7_B
FBC_CMD3
K4
CA8_B
FBC_CMD1
K3
CA9_B
FBC_CMD6
K5
CABI_B
U_MEM_SG_GDDR6
FBC_CMD10
M10
CKE_B
P/N =
FBC_CMD2
J1
RESET
K10
CLK_c
16
FBC_CLK0*
J10
CLK_t
16
FBC_CLK0
OPTION, Under DRAM
1V8_AON
C684
C679
C672
C748
U_MEM_SG_GDDR6
P/N =
C687
3
2
1
FBC_DBI[3..0]
M10D
16
FBC_DBI[3..0]
FBC_EDC[3..0]
16
FBC_EDC[3..0]
FBC_CMD[15..0]
16
FBC_CMD[15..0]
FBC_CMD32
A11
VSS
VDD
16
FBC_CMD32
A13
FBC_D[31..0]
VSS
VDD
16
FBC_D[31..0]
A2
VSS
VDD
A4
VSS
VDD
B1
VSS
VDD
B14
VSS
VDD
C10
VSS
VDD
C12
VSS
VDD
FBC_VREFC
K1
C3
VREFC
VSS
VDD
C5
VSS
VDD
D1
VSS
VDD
D12
VSS
VDD
D14
VSS
D3
VSS
E11
VSS
E4
VSS
F1
VSS
F12
VSS
F14
VSS
VDDQ
F3
VSS
VDDQ
G1
VSS
VDDQ
SNN_FBCL_TCK_M
N5
G12
TCK
VSS
VDDQ
T51
F10
SNN_FBCL_TDI_M
G14
TDI
T67
VSS
VDDQ
N10
SNN_FBCL_TDO_M
G3
TDO
VSS
VDDQ
T55
F5
SNN_FBCL_TMS_M
H11
TMS
VSS
VDDQ
T61
H4
VSS
VDDQ
L11
VSS
VDDQ
L4
VSS
VDDQ
M1
VSS
VDDQ
M12
VSS
VDDQ
M14
VSS
VDDQ
M3
VSS
VDDQ
N1
VSS
VDDQ
N12
VSS
VDDQ
N14
VSS
VDDQ
N3
VSS
VDDQ
P11
VSS
VDDQ
P4
VSS
VDDQ
R1
VSS
VDDQ
J14
FBC_ZQ_1_A
R12
ZQ_A
VSS
VDDQ
K14
FBC_ZQ_1_B
R14
ZQ_B
VSS
VDDQ
R3
VSS
VDDQ
T10
VSS
VDDQ
T12
R292
R306
VSS
VDDQ
T3
VSS
VDDQ
121_1%_04
121_1%_04
T5
VSS
VDDQ
U1
VSS
U14
VSS
V11
VSS
V13
VSS
V2
VSS
V4
VSS
G5
SNN_FBCL_RFU_A_M
RFU_A
T62
M5
SNN_FBCL_RFU_B_M
RFU_B
VPP
T58
VPP
VPP
VPP
U_MEM_SG_GDDR6
P/N =
FBVDDQ
R690
*549_1%_04
FBC_VREFC
R693
C733
R299
*931_1%_04
*820p_50V_X7R_04
1K_1%_04
Q68
G
*MTN2002ZS3
12,14,23
GPIO10_FBVREF_SEL
10,12,13,14,15,18,20,21,22,23,24,25,56,59,60,72
1V8_AON
11,12,13,14,15,16,18,19,25,59
FBVDDQ
Title
Title
Title
[17]MEMORY FBC 31..0
[17]MEMORY FBC 31..0
[17]MEMORY FBC 31..0
Size
Size
Size
Document Number
Document Number
Document Number
A3
A3
A3
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
6-71-NH5D0-D02
6-71-NH5D0-D02
6-71-NH5D0-D02
Date:
Date:
Date:
Friday, February 07, 2020
Friday, February 07, 2020
Friday, February 07, 2020
Sheet
Sheet
Sheet
2
1
FBVDDQ
A1
A14
E10
E5
H13
H2
L13
D
L2
P10
P5
V1
V14
FBVDDQ
B10
B5
C1
C11
C14
C4
E1
E14
F11
F4
H1
H14
J13
J2
K13
K2
L1
C
L14
N11
N4
P1
P14
T1
T11
T14
T4
U10
U5
1V8_AON
A10
A5
V10
V5
B
FBC_VREFC
18
A
Rev
Rev
Rev
D02
D02
D02
17
17
17
of
of
of
74
74
74
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