Clevo NH77DBQ Service Manual page 65

Frame Buffer C
5
FRAME BUFFER PARTITION C 63..32
VRAM=K4G80325FB-HC03, HC28
M9A
NORMAL
FBC_D38
B4
DQ0_A
FBC_D34 A3
DQ1_A
D FBC_D36 B3
DQ2_A
FBC_D39 B2
DQ3_A
FBC_D35
E3
DQ4_A
FBC_D32 E2
DQ5_A
FBC_D33 F2
DQ6_A
FBC_D37 G2
DQ7_A
FBC_EDC4
C2
EDC0_A
FBC_DBI4 D2
DBI0_A
FBC_W CK45 D4
WCK0_t_A
FBC_W CK45*
D5
WCK0_c_A
x16 x8
FBC_D40
B11
NC
DQ8_A
FBC_D43
A12
NC
DQ9_A
FBC_D46 B12
DQ10_A NC
FBC_D42 B13
DQ11_A NC
FBC_D44 E12
NC
DQ12_A
FBC_D45
E13
NC
DQ13_A
FBC_D47 F13
DQ14_A NC
FBC_D41 G13
DQ15_A NC
FBC_EDC5
C13
EDC1_A GND
FBC_DBI5 D13
DBI1_A
NC
FBC_W CKB45 D11
WCK1_t_A
NC
FBC_W CKB45* D10
WCK1_c_A NC
C
U_MEM_SG_GDDR6
P/N =
B
A
5
4 3
FBC_W CK45
16 FBC_W CK45
FBC_W CK45*
16 FBC_W CK45*
FBC_W CK67
16 FBC_W CK67
FBC_W CK67*
16 FBC_W CK67*
FBC_W CKB45
16 FBC_W CKB45
FBC_W CKB45*
M9B
16 FBC_W CKB45*
FBC_W CKB67
16 FBC_W CKB67
FBC_W CKB67*
NORMAL 16 FBC_W CKB67*
x16 x8
FBC_D56 U4
DQ0_B NC
FBC_D57 V3
DQ1_B
NC
FBC_D58 U3
DQ2_B NC
FBC_CMD20 H3
FBC_D59
U2
DQ3_B NC FBC_CMD28
G11
FBC_D60 P3
DQ4_B NC FBC_CMD21 G4
FBC_D61 P2
DQ5_B NC FBC_CMD29 H12
FBC_D62 N2
DQ6_B NC
FBC_CMD23 H5
FBC_D63
M2
DQ7_B NC FBC_CMD27
H10
FBC_CMD30 J12
FBC_EDC7 T2
EDC0_B GND FBC_CMD31 J11
FBC_DBI7 R2
DBI0_B
NC FBC_CMD19 J4
FBC_CMD17
J3
FBC_W CKB67
R4
WCK0_t_B NC FBC_CMD22
J5
FBC_W CKB67* R5
WCK0_c_B NC FBC_CMD26 G10
FBC_D51 U11
DQ8_B
FBC_D50
V12
DQ9_B
FBC_D48
U12
DQ10_B
FBC_D49 U13
DQ11_B
FBC_D53 P12
DQ12_B
FBC_D52 P13
DQ13_B
FBC_D55
N13
DQ14_B FBC_CMD16
L3
FBC_D54 M13
DQ15_B FBC_CMD25 M11
FBC_CMD24 M4
FBC_EDC6 T13
EDC1_B
FBC_CMD33 L12
FBC_DBI6
R13
DBI1_B FBC_CMD23
L5
FBC_CMD27 L10
FBC_W CK67 R11
WCK1_t_B FBC_CMD30 K12
FBC_W CK67* R10
WCK1_c_B
FBC_CMD31 K11
FBC_CMD19
K4
FBC_CMD17 K3
FBC_CMD22 K5
U_MEM_SG_GDDR6
FBC_CMD26 M10
P/N =
FBC_CMD18
J1
K10
16 FBC_CLK1*
J10
16 FBC_CLK1
4 3
2
FBC_DBI[7..4]
M9D
16 FBC_DBI[7..4]
FBC_EDC[7..4]
16 FBC_EDC[7..4]
FBC_CMD[31..16]
16 FBC_CMD[31..16]
FBC_CMD33
A11
VSS
16 FBC_CMD33
A13
VSS
FBC_D[63..32]
A2
VSS
16 FBC_D[63..32]
A4
VSS
B1
VSS
M9C
B14
VSS
C10
VSS
C12
VSS
K1 C3
CA0_A VREFC VSS
FBC_VREFC 17
C5
CA1_A VSS
D1
CA2_A VSS
D12
CA3_A VSS
D14
CA4_A VSS
D3
CA5_A VSS
E11
CA6_A VSS
E4
CA7_A VSS
F1
CA8_A VSS
F12
CA9_A VSS
F14
CABI_A VSS
F3
CKE_A VSS
G1
VSS
N5 SNN_FBCU_TCK_M G12
TCK VSS
T66
SNN_FBCU_TDI_M
F10 G14
TDI VSS
T53
N10 SNN_FBCU_TDO_M G3
TDO T59 VSS
F5 SNN_FBCU_TMS_M H11
TMS VSS
T49
H4
VSS
L11
VSS
L4
CA0_B VSS
M1
CA1_B VSS
M12
CA2_B VSS
M14
CA3_B VSS
M3
CA4_B VSS
N1
CA5_B VSS
N12
CA6_B VSS
N14
CA7_B VSS
N3
CA8_B VSS
P11
CA9_B VSS
P4
CABI_B VSS
R1
CKE_B VSS
FBC_ZQ_2_A
J14 R12
ZQ_A VSS
FBC_ZQ_2_B
K14 R14
ZQ_B VSS
R3
VSS
T10
VSS
R303 R286 T12
VSS
T3
RESET VSS
T5
121_1%_04 121_1%_04
VSS
U1
VSS
U14
VSS
V11
CLK_c VSS
V13
CLK_t VSS
V2
VSS
V4
VSS
G5 SNN_FBCU_RFU_A
RFU_A
T46
SNN_FBCU_RFU_B
M5
RFU_B
T48
U_MEM_SG_GDDR6
U_MEM_SG_GDDR6 P/N =
P/N =
10,12,13,14,15,17,20,21,22,23,24,25,56,59,60,72
11,12,13,14,15,16,17,19,25,59
Title Title Title
[18]MEMORY FBC 63..32 [18]MEMORY FBC 63..32 [18]MEMORY FBC 63..32
Size Size Size Document Number Document Number Document Number
6-71-NH5D0-D02 6-71-NH5D0-D02 6-71-NH5D0-D02
A3 A3 A3 SCHEMATIC1 SCHEMATIC1 SCHEMATIC1
Date: Date: Date: Friday, February 07, 2020 Friday, February 07, 2020 Friday, February 07, 2020
2
Schematic Diagrams
1
FBVDDQ
A1
VDD
A14
VDD
E10
VDD
E5
VDD
H13
VDD
H2
VDD
L13
VDD D
L2
VDD
P10
VDD
P5
VDD
V1
VDD
V14
VDD
FBVDDQ
B10
VDDQ
B5
VDDQ
C1
VDDQ
C11
VDDQ
C14
VDDQ
C4 Sheet 18 of 67
VDDQ
E1
VDDQ
E14
VDDQ
F11
VDDQ
Frame Buffer C
F4
VDDQ
H1
VDDQ
H14
VDDQ
J13
VDDQ
J2
VDDQ
K13
VDDQ
K2
VDDQ
L1
VDDQ
L14 C
VDDQ
N11
VDDQ
N4
VDDQ
P1
VDDQ
P14
VDDQ
T1
VDDQ
T11
VDDQ
T14
VDDQ
T4
VDDQ
U10
VDDQ
U5
VDDQ
1V8_AON
A10
VPP
A5
VPP
V10
VPP
V5
VPP
B
A
1V8_AON
FBVDDQ
Rev Rev Rev
D02 D02 D02
Sheet Sheet Sheet 18 18 18 of of of 74 74 74
1
Frame Buffer C B - 19