Mdp - Clevo NH77DBQ Service Manual

Schematic Diagrams

mDP

3.3VS
D
29,43,47
MINI DISPLAY PORT A(PS8330B)
C
Sheet 27 of 67
mDP
2 IGPU_LANE0P
2 IGPU_LANE0N
2 IGPU_LANE1P
2 IGPU_LANE1N
2 IGPU_LANE2P
2 IGPU_LANE2N
B
2 IGPU_LANE3P
2 IGPU_LANE3N
A
B - 28 mDP
5 4
Footprint M-SOT23-5 M-SOT23-5A
6/14 Tim
For Safety LPS. MDP_I_PWR
U47
3 1
OC# VOUT
5
VIN
C765
4 2
C1151
EN# GND
10u_6.3V_X5R_06
10u_6.3V_X5R_06
SY6288D20AAC
PCB Footprint = M-SOT23-5A
SUSB
3.3VS
11/24/2017
3.3VS
C1086 C1124
0.1u_6.3V_X5R_02 0.01u_16V_X7R_04
4/2/2018
C1103 2.2u_6.3V_X5R_04
3.3VS 3.3VS
Modify,3/19 Tim
PS8330B
37
NC
C1092 0.1u_10V_X7R_04 IN0P_R 38
IN0p
C1091 0.1u_10V_X7R_04 IN0N_R 39
IN0n
PS8330B_CFG1
40
CFG1
IN1P_R
C1094 0.1u_10V_X7R_04 41
IN1p
IN1N_R
C1093 0.1u_10V_X7R_04 42
IN1n
PS8330B
43
NC
C1096 0.1u_10V_X7R_04 IN2P_R 44
IN2p
C1095 0.1u_10V_X7R_04 IN2N_R 45
IN2n
46
NC
C1090 0.1u_10V_X7R_04 IN3P_R 47
IN3p
C1089 0.1u_10V_X7R_04 IN3N_R 48
IN3n
49
EPAD
0715
3.3VS 3.3VS
5 4
3
MDP_I_PWR
SHIELD6 GND4
COMMON
SHIELD5 GND3
PWR 20
20
GND 19
I_MDP_AUX#_R 19
18 AUX_CHN
18
I_MDP_D#2J 17 I_MDP_AUX_R
17 LANE_2N AUX_CHP 16
I_MDP_D2J 16
15 LANE_2P
15
3.3VS GND 14
14
GND 13
13
I_MDP_D#3J
12 LANE_3N
12
I_MDP_D3J 10 11 I_MDP_D#1J
LANE_3P LANE_1N
11
R341
10
I_MDP_D1J 9
LANE_1P
9
*100K_04 7 GND 8
GND
8
7
I_MDPC_CEC 6 CONFIG2
6
I_MDP_MODE 4 CONFIG1 LANE_0N 5 I_MDP_D#0J
5
4
I_MDP_D0J 3 LANE_0P
3
1 HPD 2 I_MDP_HPD_R
GND
2
R699
1
J_MDP1
1M_04 C17737-120A9-L
P/N = 6-21-11Y20-020
SHIELD2 GND2
PCB Footprint = c-909jd20fstc6-1 SHIELD1 GND1
PDB PIN:
L:Chip power down
H:Normal operation(default)
Gary 2/18/2019
3.3VS
U44
PS8330B
C1105
2 IGPU_AUX_CH_N
Mini DP Conn
24
GND
23 C1141 0.1u_10V_X7R_04 I_MDP_D0
OUT0p
C1107
22 C1136 0.1u_10V_X7R_04 I_MDP_D#0 2 IGPU_AUX_CH_P
OUT0n
21
NC
I_MDP_D1
20 C1140 0.1u_10V_X7R_04
OUT1p
I_MDP_D#1
19 C1139 0.1u_10V_X7R_04
OUT1n
18
GND
17 C1138 0.1u_10V_X7R_04 I_MDP_D2
OOUT2p
16 C1137 0.1u_10V_X7R_04 I_MDP_D#2
OUT2n
15
NC
34 I_MDP_DATA
14 C1147 0.1u_10V_X7R_04 I_MDP_D3
OUT3p
13 C1146 0.1u_10V_X7R_04 I_MDP_D#3
OUT3n
0715
34 I_MDP_CLK
DESIGN NOTE:CFG0
3.3VS
Configuration pin for automatic EQ and
Aux interception; Internal pull down at
~150Kohm,3.3V I/O
L: default, automatic EQ enable and Aux interception enable
H: automatic EQ disable and AUX interception enable
M: automatic EQ disable and AUX interception
disable,no pre-emphasis, 600mVpp swing
DESIGN NOTE:CFG1
Configuration pin for auto test and input offset
Raven add 0809
cancellation,3.3V IO, internal pull up at~150K
H: default, auto test disable and input offset cancellation
enable
L: auto test enable and input offset cancellation enable
M: auto test disable and input offset cancellation disable
3
2 1
3.3VS
D17 *4.7K_04 R688
I_MDP_D3 6 5 I_MDP_D3J *4.7K_04 R687
I_MDP_D#3 7 4 I_MDP_D#3J
8 3
I_MDP_D2 9 2 I_MDP_D2J 3.3VS
I_MDP_D#2 10 1 I_MDP_D#2J
*4.7K_04 R675
*4.7K_04 R678
*TVUDF1004AD0
D15
3.3VS
I_MDP_D0 I_MDP_D0J
6 5
I_MDP_D#0 7 4 I_MDP_D#0J *4.7K_04 R682
8 3
I_MDP_D1 9 2 I_MDP_D1J *4.7K_04 R683
I_MDP_D#1 10 1 I_MDP_D#1J
5VS
*TVUDF1004AD0
S D R722 1K_04
34 I_MDP_HPD
Q66
R677
2SK3018S3 D38
BAV99 RECTIFIER
100K_04
MDP_I_PWR
3.3VS 3.3VS
R692 R708
*100K_1%_04 100K_1%_04
I_MDP_AUX#_R
0.1u_10V_X7R_04 4 3
Q65B
MTDK3S6R
0.1u_10V_X7R_04 1 6 I_MDP_AUX_R
Q65A
R697 R704
MTDK3S6R
*100K_1%_04 100K_1%_04
5VS
5VS
R698
100K_04
4 3 I_MDP_AUX#_R
D
Q64B
MTDK3S6R Q67A G 2
S
MTDK3S6R D
Q67B
MTDK3S6R
S
I_MDP_AUX_R
6 1
Q64A
MTDK3S6R
29,31,43,44,45,46,47,70,71,72 5VS
8,9,23,24,28,29,30,31,32,33,34,35,38,39,40,42,43,44,45,47,48,52,59,70,71 3.3VS
DESIGN NOTE:PEQ
Programmalbe input equalization levels;internal pull
down at~150k ,3.3v I/O
L: default, LEQ, compensate channel loss up to 12dB at
HBR2
H: HEQ, compensate channel loss up to 15dB at HBR2
M:LLEQ, compensate channel loss up to 5dB at HBR2
Title Title Title
[27] mDP (iGPU) [27] mDP (iGPU) [27] mDP (iGPU)
Size Size Size Document Number Document Number Document Number
6-71-NH5D0-D02 6-71-NH5D0-D02 6-71-NH5D0-D02
Custom Custom Custom SCHEMATIC1 SCHEMATIC1 SCHEMATIC1
Date: Date: Date: Friday, February 07, 2020 Friday, February 07, 2020 Friday, February 07, 2020
2 1
PS8330B_CFG0
PS8330B_CFG1
D
PS8330B_PEQ
I_MDP_HPD_R
C
B
R705
100K_04
I_MDP_MODE
G 5
A
Rev Rev Rev
D02 D02 D02
Sheet Sheet Sheet 27 27 27 of of of 74 74 74