Table of Contents
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Processor 1/12
5
[17]
EDP_TXP_3
eDP PANEL
[17]
EDP_TXN_3
[17]
EDP_TXP_2
[17]
EDP_TXN_2
[17]
EDP_TXP_1
DIFF=85ohm
[17]
EDP_TXN_1
[17]
EDP_TXP_0
D
[17]
EDP_TXN_0
[17]
EDP_AUXP
[17]
EDP_AUXN
[17]
EDP_HPD
[16]
HDMI_CLOCKP
[16]
HDMI_CLOCKN
HDMI PORT
[16]
HDMI_DATA2P
[16]
HDMI_DATA2N
[16]
HDMI_DATA1P
DIFF=85ohm
[16]
HDMI_DATA1N
[16]
HDMI_DATA0P
[16]
HDMI_DATA0N
3.3VS
HDMI_CTRLCLK
R260
2.2K_04
[16]
HDMI_CTRLCLK
[16]
HDMI_CTRLDATA
R261
2.2K_04
HDMI_CTRLDATA
Enable HDMI setting
[16]
HDMI_HPD
[19]
ANX7411_TEST_R
C
R256
10K_04
3.3VS
NL40MU
BOARD_ID
R144
10K_04
NL50MU
[19]
R170
100K_04
R172
100K_04
BOARD ID
3.3VA
HIGH = NL40MU
GPP_D11
[17]
EDP_BRIGHTNESS
LOW = NL50MU
B
3.3VA
R155
*4.7K_04
GPP_E21
0 = DDP2 I2C / TBT_LSX1 pins at 1.8V
1 = DDP2 I2C / TBT_LSX1 pins at 3.3V
(internal PD 20K)
3.3VA
R242
*4.7K_04
A
GPP_D10
0 = DDP3 I2C / TBT_LSX2 pin at 1.8V
1 = DDP3 I2C / TBT_LSX2 pin at 3.3V
(internal PD 20K)
5
4
3
U21A
AC2
DDIA_TXP_3
AC1
DDIA_TXN_3
AD2
DDIA_TXP_2
AD1
DDIA_TXN_2
AF1
DDIA_TXP_1
AF2
DDIA_TXN_1
AG2
DDIA_TXP_0
AG1
DDIA_TXN_0
AJ2
DDIA_AUX_P
AJ1
DDIA_AUX
DN4
GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD
R183
100K_04
DT6
GPP_E23/DDPA_CTRLDATA
DR5
GPP_E14/DDSP_HPDA/DISP_MISCA
T12
DDIB_TXP_3
T11
DDIB_TXN_3
Y11
DDIB_TXP_2
Y9
DDIB_TXN_2
T9
DDIB_TXP_1
P9
DDIB_TXN_1
V11
DDIB_TXP_0
V9
DDIB_TXN_0
AB9
DDIB_AUX_P
AD9
DDIB_AUX
HDMI_CTRLCLK
DM29
GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN
HDMI_CTRLDATA
DK27
GPP_H17/DDPB_CTRLDATA
DG43
GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD
DG47
GPP_A21/DDPC_CTRLCLK/I2S5_TXD
DJ47
GPP_A22/DDPC_CTRLDATA/I2S5_RXD
DU8
GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD
GPP_E19
DV8
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD
DF6
GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD
GPP_E21
DD6
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD
DN23
T15
GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0#
GPP_D10
DM23
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK
DK23
GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO
GPP_D12
DN21
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI
DF43
GPP_A17/DISP_MISCC/I2S4_TXD
DF45
ANX7411_HPD
GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK
DF47
GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM
USB_OC1#
DH52
GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
USB_OC2#
DK45
GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
DM8
[17]
NB_ENAVDD
EDP_VDDEN
DN8
[17]
BLON
EDP_BKLTEN
DG10
EDP_BKLTCTL
TGL_U_IP_EXT
3.3VA
BOARD ID
HIGH = UMA
R241
GPP_D12
4.7K_04
LO = W/GPU
GPP_D12
0 = DDP4 I2C / TBT_LSX3 pins at 1.8V
1 = DDP4 I2C / TBT_LSX3 pins at 3.3
(internal PD 20K)
3.3VA
R468
*4.7K_04
GPP_E19
0 = DDP2 I2C / TBT_LSX1 pins at 1.8V
1 = DDP2 I2C / TBT_LSX1 pins at 3.3V
(internal PD 20K)
4
3
2
AY2
TCP0_TXRX_P1
AY1
TCP0_TXRX_N1
BB1
TCP0_TXRX_P0
BB2
TCP0_TXRX_N0
AM5
TCP0_TX_P1
AM7
TCP0_TX_N1
AT7
TCP0_TX_P0
AT5
TCP0_TX_N0
AP7
TCP0_AUX_P
AP5
TCP0_AUX
AT2
TYPE C+DP PORT
TCP1_TXRX_P1
AT1
TCP1_TXRX_N1
AU1
DIFF=85ohm
TCP1_TXRX_P0
AU2
Length <6000 mils
TCP1_TXRX_N0
AD5
TCP1_TX_P1
AD7
TCP1_TX_N1
AH7
TCP1_TX_P0
AH5
TCP1_TX_N0
AF7
TCP1_AUX_P
AF5
TCP1_AUX
BF1
TCP2_TXRX_P1
BF2
TCP2_TXRX_N1
BE2
TCP2_TXRX_P0
BE1
TCP2_TXRX_N0
BD7
TCP2_TX_P1
BD5
TCP2_TX_N1
AY5
TCP2_TX_P0
AY7
TCP2_TX_N0
BB5
TCP2_AUX_P
BB7
TCP2_AUX
BK1
TCP3_TXRX_P1
BK2
TCP3_TXRX_N1
BJ2
TCP3_TXRX_P0
BJ1
TCP3_TXRX_N0
BM7
TCP3_TX_P1
BM5
TCP3_TX_N1
BH5
TCP3_TX_P0
BH7
TCP3_TX_N0
BK5
TCP3_AUX_P
BK7
TCP3_AUX
TC_RCOMP_P
AN2
R430
TC_RCOMP_P
TC_RCOMP_N
AN1
TC_RCOMP
DSI_DE_TE_2
M8
R45
DSI_DE_TE_2
DP_RCOMP
AB1
R50
DDI_RCOMP
CE4
EDP_DISP_UTIL
T36
DISP_UTILS/DSI_DE_TE_1
Analog Thermal Sensor
6-17-10400-730
EWTF02-104F4F-N
TH1
100k_1%_0402_NTC
1:2 (10mils:20mils)
EW TF02-104F4F-N
1
2
3.3V
THERM_VOLT
[24]
R475
C409
20K_1%_04
*0.1u_10V_X5R_04
EVT
Th e r m a l
P C B
,
N T C
PCB
.
Title
Title
Title
[02] TGL U -A / DDI,TCP
[02] TGL U -A / DDI,TCP
[02] TGL U -A / DDI,TCP
Size
Size
Size
Document Number
Document Number
Document Number
6-71-NLx0MU-D02
6-71-NLx0MU-D02
6-71-NLx0MU-D02
A3
A3
A3
Date:
Date:
Date:
W ednesday, August 18, 2021
W ednesday, August 18, 2021
W ednesday, August 18, 2021
2
Schematic Diagrams
1
MDP_D3
[18]
MDP_D#3
[18]
MDP_D1
[18]
MDP_D#1
[18]
MDP_D2
[18]
MDP_D#2
[18]
MDP_D0
[18]
MDP_D#0
[18]
D
MDP_AUX
[18]
MDP_AUX#
[18]
Sheet 2 of 47
C
Processor 1/12
150_1%_04
100K_04
150_1%_04
B
A
R e v
R e v
R e v
D02
D02
D02
A0
Sheet
Sheet
Sheet
2
2
2
o f
o f
o f
47
47
47
1
Processor 1/12 B - 3
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