Efficiency Measurement; Table 7. Efficiency With 185 Vrms At 50 Hz; Figure 41. 230 Vrms At 50 Hz As Input - 1400 W As Output Load; Figure 42. 265 Vrms At 50 Hz As Input - 1400 W As Output Load - ST STM32F103ZE User Manual

1.4 kw digital power factor corrector
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Performance of the digital PFC

Figure 41. 230 Vrms at 50 Hz as input - 1400 W as output load

Figure 42. 265 Vrms at 50 Hz as input - 1400 W as output load

9.2

Efficiency measurement

The following tables provide information on the efficiency of the digital PFC.
Table 7.
Efficiency with 185 Vrms at 50 Hz
Percentage
Input
of target
voltage
power
25.00%
50.00%
185 Vrms
75.00%
at 50 Hz
100.00%
105.00%
48/62
www.BDTIC.com/ST
Nominal
Input power
output
(1)
[kW]
power [W]
350
0.37
700
0.73
1050
1.10
1400
1.47
1470
1.55
Doc ID 16854 Rev 1
Output
Output power
(3)
(3)
voltage [V]
[kW]
410.9
0.36
410.0
0.71
410.5
1.06
413.5
1.41
416.9
1.48
UM0877
(1)
(2)
Eff.
PF
THD [%]
97.3% 0.978
3.6
97.3% 0.995
1.5
96.4% 0.997
1.1
95.9% 0.998
0.9
95.5% 0.998
0.9

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