Introduction; Key Features; References & Specifications; Table - Alpha Data ADM-VPX3-9Z2 User Manual

ADM-VPX3-9Z2 User Manual
V1.1 - 16th January 2020

1 Introduction

The ADM-VPX3-9Z2 shall be a high performance reconfigurable 3U OpenVPX format board based on the Xilinx
Zynq Ultrascale+ range of Multiprocessor System-on-Chips (MPSoC).

1.1 Key Features

Key Features
• 3U Open VPX, compliant to VITA Standard 46.0 and 65
• FMC+ interface compliant to Vita 57.4 with high density connector
• Support for Zynq Ultrascale+ ZU9/ZU15 MPSoC in FFVB1156 package
• VPX P1 utilized according to OpenVPX payload slot profile SLT3-PAY-1F1F2U-14.2.4
• 4 optical duplex lanes at data rates of up to 10Gbps as described in Vita 66.4
• Half width P2 with 24 GPIO as described in Vita 66.4
• Processing System (PS) Block consisting of:
• Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5, Mali-400 GPU
• 1 bank of DDR4-2400 SDRAM, 1GB x72, 8GB total + ECC
• Removable microSD Flash memory
• Two Quad SPI Flash memory, up to 2Gb each
• Two USB ports to VPX P1
• Programmable Logic (PL) block consisting of:
• 600k logic cells (ZU9EG) or 747k logic cells (ZU15EG)
• 4-lanes of HSSIO on the PS block that can be configured as either:
• Dedicated 4 lane PCI-Express Gen 2 interface on the OpenVPX Data Plane
• 3 lanes on the OpenVPX Expansion Plane and 1 lane to an on board SSD drive chip
• 1 lane of PCIe on the Data Plane, 2 lanes on the Expansion Plane and 1 lane to the mSATA socket
• Two OpenVPX 1000Base-X Control Plane interfaces to VPX P1
• 2 Serial COM port interfaces to VPX P1
• Voltage and temperature monitoring
• Air-cooled and conduction-cooled configurations
1.2 References & Specifications
ANSI/VITA 46.0
ANSI/VITA 46.4
ANSI/VITA 46.6
ANSI/VITA 46.9
ANSI/VITA 48.2
ANSI/VITA 57.1
ANSI/VITA 65
ANSI/VITA 57.4
Introduction
ad-ug-1323_v1_1.pdf
VPX Baseline Standard, October 2007, VITA, ISBN 1-885731-44-2
PCI Express® on the VPX Fabric Connector, July 2010, VITA, Draft 0.15
Gigabit Ethernet Control Plane on VPX, September 2010, VITA, Draft 0.7
PMC/XMC Rear I/O Fabric Signal Mapping on 3U and 6U VPX Modules Standard,
November 2010, VITA, ISBN 1-885731-63-9
Mechanical Specifications for Microcomputers Using REDI
Conduction Cooling Applied to VITA VPX, July 2010, VITA, ISBN 1-885731-60-4
FPGA Mezzanine Card (FMC) Standard, July 2008, VITA, ISBN 1-885731-49-3
OpenVPX™ System Specification, June 2010, VITA, ISBN 1-885731-58-2
FPGA Mezzanine Card Plus(FMC+) Standard, March 2016, VITA, Draft
Table 1 : References (continued on next page)
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