Jtag Interface; On-Board Interface; Vpx Interface; Jtag Voltages - Alpha Data ADM-VPX3-9Z2 User Manual

3.4 JTAG Interface

3.4.1 On-board Interface

A JTAG boundary scan chain is connected to header J2. This allows the connection of the Xilinx JTAG cable.
The scan chain is shown in
VPX_TDI
VPX
Con
(P0) VPX_TDO
If the boundary scan chain is connected to the interface at the VPX backplane (SW3-5 is ON), header J2 should
not be used.

3.4.2 VPX Interface

The JTAG interface on the VPX backplane is normally unused. When SW3-5 is OFF (default), all JTAG signals to
P0 are left floating.
The JTAG interface can be connected to the VPX Backplane (through level-translators) by switching SW3-5 ON.

3.4.3 JTAG Voltages

The on-board JTAG scan chain uses 3.3V. The Vcc supply provided on J2 to the JTAG cable is +3.3V and is
protected by a poly fuse rated at 350mA.
The JTAG signals at the VPX interface use 3.3V signal levels and are connected through buffers to the on-board
scan chain.
The JTAG signals at the FMC interface also use 3.3V signal levels and are connected through buffers to FMC
boards scan chain.
Page 10
Figure JTAG Boundary Scan
Header
J2
HDR_TDI
Buffer
3.3V
HDR_TDO
En#
VPX_JTAG_EN#
SW3-5
Figure 4 : JTAG Boundary Scan Chain
Chain:
VREF (3.3V)
FPGA
XCZUxxEG
FFVB1156
ADM-VPX3-9Z2 User Manual
V1.1 - 16th January 2020
FMC_TDI
Buffer
3.3V
FMC+
FMC_TDO
I/F
En#
PRESENT#
Functional Description
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