Fmc+ Gpio Interface; Vpx P2 Gpio Interface; System Monitoring; Table 22 Fmc+ Groups (J1) - Alpha Data ADM-VPX3-9Z2 User Manual

ADM-VPX3-9Z2 User Manual
V1.1 - 16th January 2020

3.8.3 FMC+ GPIO Interface

The FMC+ Connector (J1) has GPIO connections arranged as follows:
Group
LA_0
LA_1
HA_0
HB_0

3.8.4 VPX P2 GPIO Interface

The P2 VPX Connector has GPIO connections arranged as follows:
Group
GPIO_0
GPIO_1

3.9 System Monitoring

The 9Z2 has the ability to monitor temperature and voltage to maintain a check on the operation of the board.
The monitoring is implemented using an Atmel AVR microcontroller (uC).
The microcontroller continually measures all voltage rails and temperature sensors and transmits the results to
the FPGA, where they are stored in blockram.
The following voltage rails and temperatures are monitored by the microcontroller:
Functional Description
ad-ug-1323_v1_1.pdf
FPGA
Name
Bank
LA(12:2)
66
LA_CC (1:0)
LA(33:19)
65
LA_CC (18:17)
HA(16:2)
HA_CC (1:0)
66,67
HA(23:18)
HA_CC (17)
HB(5:1)
HB(16:7)
HB(21:18)
64
HB_CC (0)
HB_CC (6)
HB_CC (17)
Table 22 : FMC+ Groups (J1)
FPGA
Name
Bank
48 GP(8:1)
47 GP(12:9)
Table 23 : VPX P2 GPIO Groups
Function
11 diff. Pairs / 22 single-ended
2x Regional Clocks / GPIO pairs / 4 single-ended
15 diff. Pairs / 30 single-ended
2x Regional Clocks / GPIO pairs / 4 single-ended
15 diff. Pairs / 30 single-ended
2x Regional Clocks / GPIO pairs / 4 single-ended
6 diff. Pairs / 12 single-ended
Regional Clock / GPIO pair / 2 single-ended
5 diff. Pairs / 10 single-ended
10 diff. Pairs / 20 single-ended
4 diff. Pairs / 8 single-ended
Regional Clock / GPIO pair / 2 single-ended
Regional Clock / GPIO pair / 2 single-ended
Regional Clock / GPIO pair / 2 single-ended
Function
8 diff. Pairs / 16 single-ended
4 diff. Pairs / 8 single-ended
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