Io Delay Reference Clock (Fabric_Clk); Fixed 100Mhz Reference Clock Refclk100M; Programmable Clocks (Progclk1 And Progclk2); Table 9 Ddr Refclk Connections - Alpha Data ADM-VPX3-9Z2 User Manual

3.5.1 IO Delay Reference Clock (FABRIC_CLK)

The fixed reference clock FABRIC_CLK is a differential LVDS signal.
FABRIC_CLK is used as the reference clock for the IO delay control block (IDELAYCTRL).
Signal
FABRIC_CLK

3.5.2 Fixed 100MHz Reference clock REFCLK100M

A fixed 100MHz reference clock is available on the board.
Signal
REFCLK100M[0]
REFCLK100M[1]
REFCLK100M[2]
REFCLK100M[3]

3.5.3 Programmable Clocks (PROGCLK1 and PROGCLK2)

There are two programable clock sources that are forwarded throughout the FPGA. These clocks can be
programmed via the avr2util utility contained within the Alpha Data ADM-VPX3-9Z2 SDK. PROGCLK1 and
PROGCLK2 are generated by a dedicated programmable clock generator IC and offer extremely high frequency
resolutions (1ppm increments).
Signal
PROGCLK1[0]
PROGCLK1[1]
PROGCLK1[2]
PROGCLK1[3]
Note: PROGCLK1[3:0] are all buffered copies of the same clock signal.
Signal
PROGCLK2[0]
PROGCLK2[1]
PROGCLK2[2]
PROGCLK2[3]
Note: PROGCLK2[3:0] are all buffered copies of the same clock signal.
Page 12
Frequency Target FPGA Input
300 MHz IO BANK 47
Table 9 : DDR REFCLK Connections
Frequency
100 MHz
100 MHz
100 MHz
100 MHz
Table 10 : REFCLK100M Connections
Frequency Target FPGA Input
5 - 400 MHz PS_505_MGTREFCLK_1 LVDS
5 - 400 MHz IO BANK 67
5 - 400 MHz MGTREFCLK1_228
5 - 400 MHz MGTREFCLK1_129
Table 11 : PROGCLK1 Connections
Frequency Target FPGA Input
5 - 400 MHz IO BANK 48
5 - 400 MHz IO BANK 64
5 - 400 MHz MGTREFCLK1_130
5 - 400 MHz MGTREFCLK1_229
Table 12 : PROGCLK2 Connections
IO Standard
LVDS
IO
Target FPGA Input
Standard
PS_505_MGTREFCLK_0 LVDS
IO BANK 48 LVDS
MGTREFCLK1_230 LVDS
MGTREFCLK1_128 LVDS
IO Standard
LVDS
LVDS
LVDS
IO Standard
LVDS
LVDS
LVDS
LVDS
ADM-VPX3-9Z2 User Manual
V1.1 - 16th January 2020
"P" pin "N" pin
G21 F21
"P" pin
AA27
E17
B10
N27
"P" pin "N" pin
W27 W28
R10 R9
J8 J7
J27 J28
"P" pin "N" pin
E19 D19
AK8 AK7
E27 E28
E8 E7
Functional Description
ad-ug-1323_v1_1.pdf