Module To Carrier Global Clocks (Clk_M2C); Module To Carrier Mgtref Clocks (Gbtclk_M2C); Ps_Refclk; Video_Clk - Alpha Data ADM-VPX3-9Z2 User Manual

ADM-VPX3-9Z2 User Manual
V1.1 - 16th January 2020

3.5.4 Module to Carrier Global Clocks (CLK_M2C)

A connected FMC+ board can generate a number of differential Global clocks (as per the FMC standard). They
each connect to an global clock input on the FPGA.
Signal
CLK_M2C_0
CLK_M2C_1
CLK_M2C_2
CLK_M2C_3

3.5.5 Module to Carrier MGTREF Clocks (GBTCLK_M2C)

A connected FMC board can generate a number of differential MGT Reference clocks (as per the FMC standard)
. They each connect to an MGTREFCLK input on the FPGA.
Signal
GBTCLK_0_M2C
GBTCLK_1_M2C
GBTCLK_2_M2C
GBTCLK_3_M2C
GBTCLK_4_M2C
GBTCLK_5_M2C

3.5.6 PS_REFCLK

The PS reference clock is an independent 50.0MHz reference clock. This is the master clock of the PS side of
the MPSoC.
Signal
PS_REFCLK

3.5.7 VIDEO_CLK

An optional independent 27.0MHz reference clock is provided. This can be used to clock the video sections in
the PS side of the MPSoC.
Functional Description
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Frequency
Variable
Variable
Variable
Variable
Table 13 : CLK_M2C Connections
Frequency
Variable
Variable
Variable
Variable
Variable
Variable
Table 14 : GCLK_M2C Connections
Frequency
50MHz
Table 15 : PS_REFCLK Connection
FPGA Input IO Standard
Bank 66 LVDS
Bank 66 LVDS
Bank 65 LVDS
Bank 65 LVDS
FPGA Input IO Standard
MGTREFCLK_228 LVDS
MGTREFCLK_229 LVDS
MGTREFCLK_230 LVDS
MGTREFCLK_128 LVDS
MGTREFCLK_129 LVDS
MGTREFCLK_130 LVDS
FPGA Input
PS_REF_CLK (Bank
503)
"P" pin
Y5
Y4
AF6
AE7
"P" pin
L8
G8
C8
R27
L27
G27
IO Standard pin
LVCMOS18 U24
"N" pin
AA5
Y3
AG6
AF7
"N" pin
L7
G7
C7
R28
L28
G28
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