Alpha Data ADM-VPX3-9Z2 User Manual page 4

3.10 FMC Interface and Front-Panel I/O ............................................................................................. 19
Appendix A P1 Pin Assignments ...................................................................................................................... 21
A.1 Data Plane (P1 Wafers 1-4) ......................................................................................................... 21
A.2 Data/Expansion Plane (P1 Wafers 5-8) ....................................................................................... 21
A.3 Expansion/User Plane (P1 Wafers 9-14) ..................................................................................... 22
A.4 Control Plane (P1 Wafers 15-16) ................................................................................................. 22
Appendix B P2 Pin Assignments ...................................................................................................................... 23
B.1 GPIO (P2 Wafers 4-6) ................................................................................................................. 23
Appendix C FMC Pin Assignments ................................................................................................................... 24
C.1 GPIO Pins .................................................................................................................................... 24
C.2 Clock Pins .................................................................................................................................... 26
C.3 MGT Pins ..................................................................................................................................... 27
Table 1 References ........................................................................................................................................ 1
Table 2 Build Options ..................................................................................................................................... 2
Table 3 Reset Switch Definitions .................................................................................................................... 6
Table 4 VPX Control Switch Definitions (SW3) .............................................................................................. 6
Table 5 Processor Setup Switch Definitions (SW4) ........................................................................................ 6
Table 6 Main LED Definitions ......................................................................................................................... 8
Table 7 Ethernet LED Definitions ................................................................................................................... 8
Table 8 USB LED Definitions .......................................................................................................................... 8
Table 9 DDR REFCLK Connections ............................................................................................................. 12
Table 10 REFCLK100M Connections ............................................................................................................. 12
Table 11 PROGCLK1 Connections ................................................................................................................ 12
Table 12 PROGCLK2 Connections ................................................................................................................ 12
Table 13 CLK_M2C Connections ................................................................................................................... 13
Table 14 GCLK_M2C Connections ................................................................................................................ 13
Table 15 PS_REFCLK Connection ................................................................................................................. 13
Table 16 VIDEO_REFCLK Connection .......................................................................................................... 14
Table 17 Reset Switches ................................................................................................................................ 14
Table 18 Boot Mode Selection ........................................................................................................................ 14
Table 19 Ethernet Status LEDs ...................................................................................................................... 15
Table 20 PL FPGA IO Banks .......................................................................................................................... 16
Table 21 PL MGT Links .................................................................................................................................. 16
Table 22 FMC+ Groups (J1) ........................................................................................................................... 17
Table 23 VPX P2 GPIO Groups ..................................................................................................................... 17
Table 24 Voltage and Temperature Monitors (in microcontroller) ................................................................... 18
Table 25 Temperature Limits .......................................................................................................................... 18
Table 26 System Monitor Status LEDs ........................................................................................................... 19
Table 27 Data Plane (P1 Wafers 1-4) ............................................................................................................. 21
Table 28 Data/Expansion Plane (P1 Wafers 5-8) ........................................................................................... 21
Table 29 Expansion/User Plane (P1 Wafers 9-14) ......................................................................................... 22
Table 30 Control Plane (P1 Wafers 15-16) ..................................................................................................... 22
Table 31 GPIO (P2 Wafers 4-6) ...................................................................................................................... 23
Table 32 GPIO Pins ........................................................................................................................................ 24
Table 33 Clock Pins ........................................................................................................................................ 26
Table 34 MGT Pins ......................................................................................................................................... 27
List of Tables
ADM-VPX3-9Z2 User Manual
V1.1 - 16th January 2020