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1.3.3 DRIVE CONTROL BOARD
Figure 1-7 is a functional block diagram of the drive control board. The board is mounted to the top of the drive
and connects on one end to the through bubble connector of the transducer PCB. The opposite end of the board
provides connectors for the controller data and control signals and DC power. Two additional connectors are pro-
vided for the index transducer and the actuator power driver.
Applying AC power to the drive starts the AC motor that rotates the disks. This results in the heads lifting off
the disk surface and flying above the landing zone. Applying DC power generates a power on reset by the POR cir-
cuit, which resets the microprocessor and all drive logic. Until the rotational speed of the disks exceeds 2,000 RPM,
the RESET ONE SHOT keeps the microprocessor reset. Then, the microprocessor waits until the speed reaches ap-
proximately 3,000 RPM via the -INDEX line, at which point it waits two seconds for the heads to contact the land-
ing zone. Next, the microprocessor calibrates the PI and P2 signals by computing center values.
The heads then perform 100 five track seeks and continue to servo on the last seeked track for greater than one
second to compute the Null Current Value. The Null Current Value is the current required to keep the actuator mo-
tionless. Following this, the heads single step out to Thack 0, then the microprocessor sets READY and SEEK COM-
PLETE. The heads continue to servo on Thack 0 until interrupted by a command from the controller.
When DRIVE SELECT "X" is driven true and matches the drive select jumper, the drive select logic enables
the interface logic to gate control and data signals to and from the drive. The drive will read or write data on the
selected head at the present track depending on the state of the WRITE GATE line. The read/write circuits transfer
the MFM data as required.
The drive may be commanded to move the heads by receiving step pulses. The pulses can be sent in one of two
modes:
1.
Normal mode, in which the step pulses are sent slower than every 1.5 msec.
2.
Buffered mode, in which the step pulses are sent faster than every 2001lsec.
USER
PWR
SUPPLY
+5
~
~
-~
I
POWER
FILTERS
&
REG
t
POWER
+24
~
12
r
t
+
5
~ ~
ACTUATOR
POWER
RESET
---
ON
RESET
t
r
MICRO
h
PROCESSOR
h
SERVO
/
"
/
)
ACTUATOR
f-+-
CONVERSION
DRIVE
,
I
,
t
READ
DATA
TO
CON TROLLER
INTERFACE
&
DRIVE
SELECT
J
WRITE
DATA
FIGURE 1-7
DRIVE CONTROL PCBA BLOCK DIAGRAM
1-9
TO
ARM
STACK
REV A (01/84)
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