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+
DRIVE SELECT
+
WRITE GA TE 10
9
+SEEK
COIIPLETE
+SV
+24
LI
~-------
__ DETECT
R8
~-------.-
__ TO WRITE CURRENT
+5V
WRITE TOGGLE FF
Rll
WRITE
DRIVER
FIGURE 1-28
WRITE ENABLE SWITCH
03
RIS
Q2
6
lOV
CR3
AI7
CRI6
RlO
R/W
HEAD
HEAD
SWITCH
+24V
RPI
Figure 1-29 illustrates the operation of the write data receiver found on Figure 2-2, B5 and the write driver
found on Figure 2-3, B3. When + WRITE enables the differential line receiver U2J, a 75107, the differential MFM
WRITE DATA signal terminated by R23 and R24 converts to a TTL signal at output pin 9. When the +MFM
WRITE DATA signal goes more positive than -MFM WRITE DATA signal, the TTL output will
s~itch
HI. Since
+ WRITE removes the preset and clear inputs from the write data flip-flop U4C, the flip-flop will toggle to the op-
posite state. If we say the Q output (4C-5) switches LO, then Q2-2 goes LO and turns on this side of the driver.
Current will flow from the constant current source through the transistor, through CR4, through the head
switch diode, through coil A of the head, and to ground through the head select switch 5A. When the next pulse ar-
rives (4C-3) the
FIF
switches states, Q2 (1,2,3) conducts, and current flows through head coil B. Resistor R32 is used
to prevent oscillations in the head coil by providing a damping path. Resistors R30 and R31 will cause diodes CR4
and CR5 to be reverse biased when the write current stops. Inductor L1 and resistor pack RPI cause the head switch-
ing diodes of the unselected heads to be reversed biased.
The head select switch UA3 is a one of ten decoder. Based on the binary configurations of the three input bits;
+ HEAD 2°,2
1 ,
and 22; only one of the outputs will be LO. This LO provides the ground path for current through
the selected head. During seeks the chip deselect (pin 12) will deselect all the outputs. Upon completion of the seek
the outputs will be re-enabled.
REV A (01/84)
1-26
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